Capacitance variability of short range interconnects

Abstract

End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layout sensitive and worsens with reduction in feature size, and together with the increasing device variability requires inclusion in statistical models of standard cells from the 45 nm node onwards. If LER does not improve then, for example, by the 22 nm node, short parallel lines on metal 1 are predicted to have 12% variability and, depending on layout, SRAM bit line capacitance 7% variability.

Influence of parasitic memory effect on single-cell faults in SRAMs

“…C L is a function of H, W, T and S. H is the thickness of the dielectric layer between metal layers, W is the width of the metal line, T is the thickness of the metal line and S is the spacing between the parallel lines [4], [8]. In advanced MOS technologies, the line-to-line capacitance is comparable to, or larger than the line-to-ground capacitance [3].…”

Parasitic memory effect in CMOS SRAMs

“…where W is the width of the metal line, T is the thickness of the metal line, H is the thickness of the dielectric layer between metal layers, and S is the spacing between the parallel lines [5], [6], [11].…”

“…At the detection stage, seq {op 6 } is applied to the cell and the transition induces delay, which is propagated to and observed at the output. The input transition is initiated by op 5 and detected by op 6 , and R cr is 248kΩ. We associate to this defect the Detection Interval DI defined below as: …”

Discrete-Dopant-Fluctuated Transient Behavior and Variability Suppression in 16-nm-Gate Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

“…12) The fluctuation of characteristic is caused not only by variation in average doping density, which is associated with a fluctuation in the number of impurities, but also by the particular random distribution of impurities in the channel region. Diverse approaches have recently been proposed to study fluctuation-related issues in semiconductor devices [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] and circuit. [31][32][33][34][35][36] However, little attention has been focused on the existence of transient characteristic fluctuations in the active devices due to random dopant placement.…”

“…Moreover, due to the randomness of dopant position in the devices, the fluctuation of device gate capacitance is nonlinear and difficult to model with the current compact models. 24) In this study, we propose a large-scale statistically sound device-circuit-coupled simulation approach to analyze the random dopant effect in nanoscale complementary MOS (CMOS) circuits, whereby the discrete-dopant-number-and discrete-dopant-position-induced fluctuations can be captured concurrently. Based on the statistically generated large-scale doping profiles, device simulation is performed by solving a set of three-dimensional (3D) drift-diffusion equations with density-gradient quantum corrections meth-od, [37][38][39][40] which is conducted using a parallel computing system.…”