Capacitance–voltage characteristics and device simulation of bias temperature stressed a-Si:H TFTs

Tang, Zhao; Wie, C. R.

doi:10.1016/j.sse.2009.09.025

Cited by 19 publications

(11 citation statements)

References 28 publications

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“…As illustrated in Figure 3d, at the low-gate-bias regime (V gs < 15 V), as the gate bias increased, the trap density was estimated to be as low as ~10 12 states eV −1 cm 2 , but it increased rapidly to ~10 13 states eV −1 cm 2 . However, at the high-gate-bias regime (V gs > 15 V), it was estimated to be as high as ~10 14 states eV −1 cm 2 , but it slowly increased. Although trap states are literally trap states, the trap states in ZnO films can act as conduction states in the forbidden gap.…”

Section: Resultsmentioning

confidence: 99%

“…Thus, the in-depth understanding of charge-transport behaviors' near-threshold voltage and the definition of the threshold voltage of TFTs are quite important. Indeed, due to localized states in the disordered oxide semiconductors, the charge-transport characteristics of TFTs are severely affected by interface and semiconductor trap states [14,15]. As a result, it is difficult to determine the conduction states and threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

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Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

Yoon

2023

Materials

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In this paper, we present a threshold-voltage extraction method for zinc oxide (ZnO) thin-film transistors (TFTs). Bottom-gate atomic-layer-deposited ZnO TFTs exhibit typical n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, unreliable threshold voltage. We posit that this obscure threshold voltage is attributed to the localized trap states of ZnO TFTs, of which the field-effect mobility can be expressed as a gate-bias-dependent power law. Hence, we derived the current–voltage relationship by dividing the drain current with the transconductance to rule out the gate-bias-dependent factors and successfully extract the reliable threshold voltage. Furthermore, we investigated the temperature-dependent characteristics of the ZnO TFTs to validate that the observed threshold voltage was genuine. Notably, the required activation energies from the low-temperature measurements displayed an abrupt decrease at the threshold voltage, which was attributed to the conduction route change from diffusion to drift. Thus, we conclude that the reliable threshold voltage of accumulation-mode ZnO TFTs can be determined using a gate-bias-dependent factor-removed current–voltage relationship with a low-temperature analysis.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

Yoon

2023

Materials

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“…8(a) have shown same nature for all the temperature variations. It is also seen that C GS is greater than that of C GD , which can be attributed to uneven distribution of charge on application of drain source bias [42]. The highest value of C GS & C GD is 280 fF and 266 fF respectively, which is very less and beneficial for circuit designing.…”

Section: Impact Of Temperature On the DC Analog And Rf Parametersmentioning

confidence: 95%

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

Jain

Singh

Sharma

et al. 2022

Silicon

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This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of -0.29 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 10 9 , intrinsic gain (A v ) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are obtained for D t of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of -0.26 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 10 10 , A v of 175.69 dB and GFP of 2.39 GHz. In order to investigate device thermal reliability and stability, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T) . It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance. This analysis confirms the potential of a-ITZO TFTs to realize high performance analog/RF circuits.

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“…8 (a) have shown same nature for all the temperature variations. It is also seen that 𝐶 𝐺𝑆 is greater than that of 𝐶 𝐺𝐷 , which can be attributed to uneven distribution of charge on application of drain source bias [39]. The highest value of 𝐶 𝐺𝑆 & 𝐶 𝐺𝐷 is 280 fF and 266 fF respectively, which is very less and beneficial for circuit designing.…”

Section: Impact Of Temperature On the DC Analog And Rf Parametersmentioning

confidence: 95%

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

Jain

Singh²,

Sharma

et al. 2021

Preprint

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This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡 ) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of (- 0.29) V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 109 , intrinsic gain (𝐴𝑉) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are offered for dielectric thickness of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of (-0.26 V), 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 1010 , (𝐴𝑉) of 175.69 dB and GFP of 2.39 GHz. For device reliability and stability study, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T). The results obtained are promising to meet the current display industry requirement. It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance.

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Capacitance–voltage characteristics and device simulation of bias temperature stressed a-Si:H TFTs

Cited by 19 publications

References 28 publications

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

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