Capacitive coupling noise in high-speed VLSI circuits

Heydari, Payam; Pedram, Massoud

doi:10.1109/tcad.2004.842798

Cited by 57 publications

(22 citation statements)

References 19 publications

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“…However for most on-chip lines or interconnects, capacitive effects are still the dominant factor [11,12]. Hence, in the analysis, inductance effects are ignored and capacitive coupling is assumed as the dominant mechanism for crosstalk.…”

Section: Analysis Single Event Crosstalkmentioning

confidence: 99%

“…The interaction caused by parasitic coupling between wires, that is known as crosstalk, may cause undesired effects such as positive and negative glitches, overshoot, undershoot, signal delays or even delay reduction [11,12]. If crosstalk effects on the victim net (affected line) are large, they can propagate into storage elements that are connected to victim line and can cause logic errors.…”

Section: Introductionmentioning

confidence: 99%

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Single Event Soft Error Mechanisms

Sayıl

2016

Soft Error Mechanisms, Modeling and Mitigation

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It has been reported that advanced processors with large multimegabit-embedded SRAM can easily have soft failure rates in excess of 50,000 FIT at terrestrial level [1]. The same error rate can also be achieved for standard high-density ASIC designs at 90 nm and below in [2].For single-chip consumer applications, this error rate may not still be important for most designers, but for high-reliability systems composed of multi-chip assemblies such a rate becomes intolerable [1]. Hence, for mission-critical or high-reliability applications such as military, avionics [3], medical systems [4], etc., other sources for such errors also need to be included in reliability analysis in addition to SETs. These additional error sources include SE soft delays [5], radiation induced clock jitters and clock pulses [6], SE crosstalk noise pulses [7][8][9], and finally the SE crosstalk delay [10] that has been reported relatively recently.All these errors occur under specific conditions: Soft delay effect occurs when high-energy particle hits the drain node of a CMOS gate's transistor while signal at the output is transitioning. SE clock jitter occurs when particles inject charge onto clock circuit nodes during clock edge present. An energetic particle strike on clock circuit nodes can also create a "false clock pulse" which can be interpreted as a legitimate clock pulse. At last, the SE crosstalk noise and crosstalk delay effects occur via interconnect cross-coupling. The interconnect coupling effects can cause SETs to contaminate electronically unrelated circuit paths which can in turn increase the "SE susceptibility" of CMOS circuits.With newer technologies the severity of these mechanisms increase as transistor sizes reduces and working frequencies increase.

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Section: Analysis Single Event Crosstalkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Single Event Soft Error Mechanisms

Sayıl

2016

Soft Error Mechanisms, Modeling and Mitigation

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“…The per unit length (p.u.l) parameters RLC of equivalent line (Fig 4) for each mode are computed from the p.u.l. parameters of the coupled lines (2). …”

Section: Coupling Modelingmentioning

confidence: 99%

“…Reference [1] incorporates a model order reduction technique to efficiently simulate the on-chip interconnects as distributed RC sections. Until recently, most works have been limited to RC networks leaving an inherent unpredictability in the design process where inductive effects are suspected [2]. Operating frequencies that have increased over the past decade are expected to maintain this increasing behavior over the next decade approaching 10GHz by the year 2012.…”

Section: Introductionmentioning

confidence: 99%

Additivity of capacitive and inductive coupling in submicronic interconnects

Lorival

Deschacht

Quéré

et al. 2006

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.

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Abstract-Constant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations.

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“…The interaction caused by parasitic coupling between wires, which is generally known as crosstalk, may cause undesired effects such as positive and negative glitches, overshoot, undershoot, signal delays or even delay reduction [9][10][11]. If crosstalk effects on the victim (affected) net are large, they can propagate into storage elements that connected to victim line and can cause permanent errors.…”

Section: Introductionmentioning

confidence: 99%

Single event crosstalk prediction in nanometer technologies

Sayıl

Boorla

2011

Analog Integr Circ Sig Process

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As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-p model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.

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Capacitive coupling noise in high-speed VLSI circuits

Cited by 57 publications

References 19 publications

Single Event Soft Error Mechanisms

Single Event Soft Error Mechanisms

Additivity of capacitive and inductive coupling in submicronic interconnects

Single event crosstalk prediction in nanometer technologies

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