Capacitive Synaptor with Gate Surrounding Semiconductor Pillar Structure and Overturned Charge Injection for Compute‐in‐Memory

Abstract

The newly suggested synapse capacitor (synaptor) in this work has a cross‐point feature, enabling implementation at a feature size of 4F2. This synaptor has a gate surrounding semiconductor pillar (GSSP) structure with overturned charge injection (OCI) scheme to ensure high capacitive memory window. Sentaurus TCAD simulation tools are used to demonstrate the process feasibility and device characteristics. Two important process parameters are optimized to show the best characteristics; overlap height (Hov) and channel pillar height (Hch). An OCI‐GSSP device that has an aspect ratio of 10 and the minimal overlap height shows the highest Con/Coff over 5 in 40 nm wordline and BL pitch. It is the highest value and the smallest unit device size among the capacitive synapses that have been reported up to now. Advantages of scaled OCI‐GSSP devices are appealed through subarray circuit simulation. The subarray composed of OCI‐GSSP synaptor can calculate one vector‐matrix multiplication operation with energy under 200 fJ and column delay of 3 ns, and result in sufficient signal margin of 275 mV.