2020
DOI: 10.1109/led.2020.3014431
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Capacitive Trench-Based Charge Transfer Device

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Cited by 10 publications
(8 citation statements)
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“…The n-well doping profile has a maximum doping concentration at about 1 µm depth, which makes the charge storage possibly deep in the volume of the silicon, far from the surface. The n-well doping concentration has been adjusted in a way to allow for a full depletion of the buried layer, as described in the reference [15]. The n-well storage and transfer volume are delimited by a p+ pinning implantation on the top, as well as by the p-epitaxial layer at the bottom and laterally by the CDTI gates.…”
Section: Methodsmentioning
confidence: 99%
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“…The n-well doping profile has a maximum doping concentration at about 1 µm depth, which makes the charge storage possibly deep in the volume of the silicon, far from the surface. The n-well doping concentration has been adjusted in a way to allow for a full depletion of the buried layer, as described in the reference [15]. The n-well storage and transfer volume are delimited by a p+ pinning implantation on the top, as well as by the p-epitaxial layer at the bottom and laterally by the CDTI gates.…”
Section: Methodsmentioning
confidence: 99%
“…A trench CCD has been proposed in 1989 [14] where electrons are carried between two trenches, but the development seems to be canceled. Then, a CCD-on-CMOS trench structure based on CDTI has been developed in 2020 [15], and this device is used for this study. In this particular concept, CDTIs shape the electrostatic potential, leading to carrier displacement in a buried channel mode.…”
Section: Introductionmentioning
confidence: 99%
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“…In response to the above application requirements, many scholars have carried out research on high-performance photodetectors. Using single-photon detection technology can greatly improve the detection efficiency of optoelectronic devices, such as photomultiplier tubes (PMTs) [ 26 , 27 ], charge-coupled devices (CCDs) [ 28 ], and avalanche photodiodes (APDs) [ 29 , 30 ]. However, PMT and CCD are not compatible with the standard integrated circuit design process, which limits the application of these devices.…”
Section: Introductionmentioning
confidence: 99%
“…However, there are some restrictions on using the existing solution in advanced lithography systems. To achieve high charge transfer efficiency, CCDs require specialized fabrication processes [12]- [14]. For APS arrays can be made with processes which is compatible to CMOS process, the photodiodes are not optimized for electron beam collection [15], [16].…”
Section: Introductionmentioning
confidence: 99%