Capacitorless LDO with fast transient response based on a high slew-rate error amplifier

Răducan, Cristian

doi:10.1109/smicnd.2015.7355234

Cited by 8 publications

(8 citation statements)

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“…The final Section comprises a comprehensive comparison with state-of-the-art and a summary of main points presented in, and of conclusions drawn from, this work. It employs a novel OTA, derived from the OTA proposed in [2] by employing two techniques for achieving a higher transconductance we described in [12]: 1) the current recycling introduced in [11] -implemented here by using two additional transistors for each input (M1A_B & M2A_B) and the current mirrors M3A-M3B & M4A-M4B.…”

mentioning

confidence: 99%

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

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This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only 0.7µA quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in 1µs the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figureof-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

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confidence: 99%

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

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“…The operational transconductance amplifier (OTA) shown in Fig. 4 employs a recycled folded cascode topology [8] and adaptive biasing to achieve large values for the low-frequency gain and slew rate (SR) [4].…”

Section: ) Error Amplifier With High Slew Ratementioning

confidence: 99%

“…The input stage is formed by two pairs of matched crosscoupled transistors, M1a-M1b and M2a-M2b, and two levelshifters, M13a and M13b, and operates in class AB [9]. Assuming that transistors M1a, M1b, M2a, M2b, M13a, M13b work in the saturation region, the output current is a 4 th order function of the differential input voltage, Vid = VInP-VInM [4]:…”

Section: ) Error Amplifier With High Slew Ratementioning

confidence: 99%

“…However, the output voltage overshoot remains relatively large and the maximum CL value the LDO proposed in [2] is stable for is only 100 pF. The solutions proposed in [3] and [4] use operational transconductor amplifiers with enhanced slew rate and adaptive biasing; they require less quiescent current and are more effective in reducing the output voltage overshoot than the LDO proposed in [2], but they, too, cannot handle load capacitors larger than 100 pF.…”

Section: Introductionmentioning

confidence: 99%

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Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

et al. 2022

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This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for CL = 0 and under 60 mV for CL =1 μF, when the load current varies between 1 μA and 100 mA in 1 μs. The LDO requires only 6.2 μA of quiescent current and occupies 0.018 mm 2 of die area.INDEX TERMS any load capacitor, fast-transient LDO, high slew-rate error amplifier, fast response to load transients

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“…adding a buffer to the output stage of the error amplifier to extend the loop bandwidth [11], [12]; III. extending the bandwidth of the error amplifier by changing its configuration [13], [14]; IV. providing a lower impedance pass transistor stage to extend the loop bandwidth [15]- [17].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Quiescent Current LDO with FVF-Based Load Transient Enhanced Circuit

Mii

Nagahama

Watanabe

2020

IEICE Trans. Electron.

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This paper proposes an ultra-low quiescent current lowdropout regulator (LDO) with a flipped voltage follower (FVF)-based load transient enhanced circuit for wireless sensor network (WSN). Some characteristics of an FVF are low output impedance, low voltage operation, and simple circuit configuration [1]. In this paper, we focus on the characteristics of low output impedance and low quiescent current. A load transient enhanced circuit based on an FVF circuit configuration for an LDO was designed in this study. The proposed LDO, including the new circuit, was fabricated in a 0.6 μm CMOS process. The designed LDO achieved an undershoot of 75 mV under experimental conditions of a large load transient of 100 μA to 10 mA and a current slew rate (SR) of 1 μs. The quiescent current consumed by the LDO at no load operation was 204 nA.

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Capacitorless LDO with fast transient response based on a high slew-rate error amplifier

Cited by 8 publications

References 5 publications

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

Ultra-Low Quiescent Current LDO with FVF-Based Load Transient Enhanced Circuit

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