Proceedings of the 26th Edition on Great Lakes Symposium on VLSI 2016
DOI: 10.1145/2902961.2902992
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Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

Abstract: Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with the efficiency of the Compact Digital Waveform (CDW) representation. That way, we capture the true workload-dependent BTI-induced degradation of selected CPU components. First, we show that existing … Show more

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Cited by 8 publications
(10 citation statements)
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“…Hence, evaluating the degradations across the complete net instead of on individual transistors is essential to observe the real impact on the circuit critical paths. In contrast with previous works that study individual transistors or small benchmark circuits, we align ourselves with studies that tackle the complexity of large circuits representative of real systems [4], [12].…”
Section: Bti Degradationmentioning
confidence: 99%
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“…Hence, evaluating the degradations across the complete net instead of on individual transistors is essential to observe the real impact on the circuit critical paths. In contrast with previous works that study individual transistors or small benchmark circuits, we align ourselves with studies that tackle the complexity of large circuits representative of real systems [4], [12].…”
Section: Bti Degradationmentioning
confidence: 99%
“…Stamoulis et al introduced workload dependencies into CETmap based BTI modeling [4]. Their work can be potentially applied to any workload and circuit type.…”
Section: Bti Degradationmentioning
confidence: 99%
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