Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Wong, H.-S. Philip; Mitra, Subhasish; Akinwande, Deji; Beasley, Cara; Chai, Yang; Chen, Hongyu; Chen, Xiangyu; Close, Gael F.; Deng, Jie; Hazeghi, Arash; Liang, Jiale; Lin, Andy; Liyanage, Luckshitha Suriyasena; Luo, Jianjun; Parker, Jason; Patil, Nishant; Shulaker, Max M.; Wei, Hai; Wei, Lan; Zhang, Jie

doi:10.1109/iedm.2011.6131594

Cited by 27 publications

(12 citation statements)

References 22 publications

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“…I. INTRODUCTION ARBON nanotube field-effect transistors (CNFETs) based on single-walled semiconducting CNTs have been among the foremost candidates to complement Si and extend CMOS technology scaling in the sub-10-nm technology nodes [1][2][3]. One of the dominant factors impeding further scaling of Si metal-oxide-semiconductor field-effect transistors (MOSFETs) is the short-channel effect (SCE), which causes FETs at short gate lengths to be difficult to turn off, consequently consuming too much power [4].…”

mentioning

confidence: 99%

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

Lee

Pop

Franklin

et al. 2015

IEEE Trans. Electron Devices

210

131

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Abstract-We presents a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltage characteristics. The features of the model include: (i) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; (ii) carrier effective mobility and velocity depending on the CNT diameter; (iii) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; (iv) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNFET model captures dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes.Index Terms-carbon nanotube (CNT), carbon-nanotube fieldeffect transistor (CNFET or CNTFET), compact model, technology assessment.

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mentioning

confidence: 99%

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

Lee

Pop

Franklin

et al. 2015

IEEE Trans. Electron Devices

210

131

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“…Carbon Nanotube Field Effect Transistors (CNFETs) appear to be one of the promising successors to silicon CMOS due to their superior device characteristics [Avouris et al 2007;Zhang et al 2012;Wong et al 2011;Wei et al 2009a]. A representative CNFET structure is shown in Figure 1(a).…”

Section: Introductionmentioning

confidence: 98%

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Bobba

Zhang

Gaillardon

et al. 2014

J. Emerg. Technol. Comput. Syst.

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The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carbon Nanotube (CNT) imperfections. Various layout schemes are studied for enhancing the yield of CNFET standard cell library. With the help of existing ASIC design flow, we perform system-level benchmarking of CNFET circuits and compare them to CMOS circuits at various technology nodes. With CNFET technology, we observe maximum performance gains for circuits with gate-dominated delays. Averaged across various benchmarks at 16 nm, we report 8× improvement in Energy-Delay-Product (EDP) with CNFET circuits when compared to CMOS counterpart. We also study the performance of a complete OpenRISC processor, where we see 1.5× improvement in EDP over CMOS at 16 nm technology node. Voltage scaling enabled by CNFETs can be explored in the future for further performance benefits. . 2014. System level benchmarking with yield-enhanced standard cell library for carbon nanotube VLSI circuits. ACM

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“…Beyond 45 nm, many devices exhibit Schottky characteristic at source and drain contacts such as SiNWs [4], carbon nanotubes [5], and graphene [6]. These devices have ambipolar behavior, i.e., they support the flow of both n-type and p-type carriers.…”

Section: Introductionmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

Gaillardon

Micheli

2015

IEEE Trans. Nanotechnology

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Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

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Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Cited by 27 publications

References 22 publications

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

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