2005
DOI: 10.1016/j.microrel.2004.12.016
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Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

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Cited by 11 publications
(6 citation statements)
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“…[11][12][13] Figure 1 is a schematic illustration of carrier separation and four-point wafer bending. [11][12][13] Figure 1 is a schematic illustration of carrier separation and four-point wafer bending.…”
Section: Methodsmentioning
confidence: 99%
“…[11][12][13] Figure 1 is a schematic illustration of carrier separation and four-point wafer bending. [11][12][13] Figure 1 is a schematic illustration of carrier separation and four-point wafer bending.…”
Section: Methodsmentioning
confidence: 99%
“…Transconductance degradation (Δg m ) due to TG at or very close to the Si/IL interface and its correlation to ΔV T is extracted from transfer IV measured in MSM mode. Stress Induced Leakage Current (SILC) during PBTI stress, presumably due to TG near the IL/HK interface [13] or in the HK bulk [14], is measured using carrier separation technique [15] in MSM mode. Process induced (pre-stress) gate insulator traps in N and P MOSFETs (that facilitates TP) are estimated using flicker noise [5], [16], [17].…”
Section: Bti Measurement and Analysismentioning
confidence: 99%
“…1 eV below the conduction band edge which facilitate electron transfer into the conduction band. 1,2 However, hole conduction has also been reported in HfO 2 and TiO 2 , 3 and hence it was postulated that a hole current may be induced via injection from the Si to the TiO 2 surface, and that this would be facilitated by rendering the metal overlayer on the TiO 2 negative. By fabricating the metal overlayer in the form of a grid, holes may be generated at the open surface of the TiO 2 and such carriers may be available for reactions in an external fluid.…”
mentioning
confidence: 99%