Case Study: Soft Error Rate Analysis in Storage Systems

Mullins, Brian; Asadi, Hossein; Tahoori, Mehdi B.; Kaeli, David; Granlund, Kevin; Bauer, R. S.; Romano, S.

doi:10.1109/vts.2007.21

Cited by 4 publications

(3 citation statements)

References 13 publications

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“…This work is done based on our collaboration with a major industrial information computing system manufacturer. This work complements the work done in [7], which analyzed field data for computing SER in FPGA-based designs. Since the internal structure of the microprocessor is not observable at the system level, determining soft error rates using field data for microprocessors is more challenging compared to performing the same study for FPGA-based designs.…”

Section: Introductionsupporting

confidence: 53%

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A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems

Shazli

Abdul-Aziz

Tahoori

et al. 2008

2008 IEEE International Test Conference

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Section: Introductionsupporting

confidence: 53%

“…Field data analysis is traditionally used in industry to evaluate system failure rates, monitor system reliability, and conduct long-term trend analysis to identify the need for future design changes [ [7]. In the case of FPGAs, the configuration bits can be read out and checked for bit-flips.…”

Section: Seus In the Fieldmentioning

confidence: 99%

A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems

Shazli

Abdul-Aziz

Tahoori

et al. 2008

2008 IEEE International Test Conference

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“…To our best knowledge, this is the first attempt to validate a system-level soft error modeling tool using real and comprehensive field failure data. Preliminary results of this case study were presented in [28].…”

mentioning

confidence: 99%

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi¹,

Tahoori

Mullins³

et al. 2007

IEEE Trans. Nucl. Sci.

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Abstract-Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the Logical Unit Module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).Index Terms-Error analysis, field programmable gate arrays (FPGA), information systems, logic circuit fault tolerance, reliability estimation, reliability modeling, SRAM chips (SRAM-based FPGAs).

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