2013 IEEE 27th International Symposium on Parallel and Distributed Processing 2013
DOI: 10.1109/ipdps.2013.107
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CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Abstract: Abstract-Aggressive silicon process scaling over the last years has made transistors faster and less power consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors.In this work, we present CASTED, a Core-Adaptive Software Transient Error Detection methodology that focuses on improving the impact of error detection over… Show more

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Cited by 4 publications
(3 citation statements)
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“…For instance, the approach presented in [22,23] applies full duplication and full comparison in the compiled code, whereas the approach of [24] reduces the number of compared instructions. CASTED [25] proposes a compiler-based technique to distribute error detection overhead across core/clusters, which is applicable to tightly coupled cores and clustered VLIWs. Although static approaches do not require additional hardware, the code size, storage and energy consumption are increased.…”
Section: Related Workmentioning
confidence: 99%
“…For instance, the approach presented in [22,23] applies full duplication and full comparison in the compiled code, whereas the approach of [24] reduces the number of compared instructions. CASTED [25] proposes a compiler-based technique to distribute error detection overhead across core/clusters, which is applicable to tightly coupled cores and clustered VLIWs. Although static approaches do not require additional hardware, the code size, storage and energy consumption are increased.…”
Section: Related Workmentioning
confidence: 99%
“…CASTED [29] is implemented at the backend stage of the compilation process; it uses the GCC-4.5.0 [30] compiler framework. This technique includes two passes, one for error detection and another one for recovery.…”
Section: ) Thread-level Replication (Tlr)mentioning
confidence: 99%
“…Depending on the accuracy of the simulation, this can vary from extremely slow (e.g., at the RTLlevel), to quite slow (tens/hundreds of MIPS) for the fastest emulators. This is a very popular technique and has been used in several studies, including [5,11,13,18,20,22,23,27,28,36,39]. 3.…”
Section: Introduction and Related Workmentioning
confidence: 99%