CCF-LRU: a new buffer replacement algorithm for flash memory

Li, Zhi; Jin, Peiquan; Su, Xuan; Cui, Kai; Yue, Lihua

doi:10.1109/tce.2009.5277999

Cited by 103 publications

(51 citation statements)

References 8 publications

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“…We evaluated 3bit ARW-B, 3bit ARW-I and 2bit ARW-I with three previous methods, that is, LRU, RRIP and CCFLRU [12]. CCFLRU is a competitive baseline originally designed to reduce writebacks to SSD.…”

Section: Discussionmentioning

confidence: 99%

“…However, it doesn't distinguish clean and dirty states of pages. Cold-Clean-First LRU (CCFLRU) [12] policy enhanced CFLRU and LRU-WSR methods by differentiating clean pages into cold and hot ones, and evicting cold clean pages first and delaying the eviction of hot clean pages. AD-LRU [21] sets the lowest limit for the size of the cold list.…”

Section: Related Workmentioning

confidence: 99%

“…The other challenge is the limited lifetime due to the endurance constraint. For NAND Flash, the number of erase operation allowed to be performed for each block ranges from 10 4 to 10 6 [12], while for PCM, it can tolerate 10 8 − 10 15 writes per cell [13]. Once the endurance constraint is exceeded, the block or cell will be worn out, making the memory unreliable.…”

Section: Introductionmentioning

confidence: 99%

“…Recently a few cache management techniques [18]- [20] have been proposed to mitigate the write overhead of PCM, but most of them are performed on PCM itself, without optimizing the write traffic sent from LLC. In addition, there are some buffer management policies [12], [21], [22] that can reduce the writebacks to NAND Flash, but they fall short in efficiency and are difficult to implement on chip. To • The base ARW policies, which consider the asymmetric costs of read and write operations by setting different evicting priorities, are proposed to minimize the write traffic.…”

Section: Introductionmentioning

confidence: 99%

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ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

Zhang¹,

Duan²,

Yang³

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe write operations on emerging Non-Volatile Memory (NVM), such as NAND Flash and Phase Change Memory (PCM), usually incur high access latency, and are required to be optimized. In this paper, we propose Asymmetric Read-Write (ARW) policies to minimize the write traffic sent to NVM. ARW policies exploit the asymmetry costs of read and write operations, and make adjustments on the insertion policy and hit-promotion policy of the replacement algorithm. ARW can reduce the write traffic to NVM by preventing dirty data blocks from frequent evictions. We evaluate ARW policies on systems with PCM as main memory and NAND Flash as disk. Simulation results on an 8-core multicore show that ARW adopted on the last-level cache (LLC) can reduce write traffic by more than 15% on average compared to LRU baseline. When used on both LLC and DRAM cache, ARW policies achieve an impressive reduction of 40% in write traffic without system performance degradation. When employed on the on-disk buffer of the Solid State Drive (SSD), ARW demonstrates significant reductions in both write traffic and overall access latency. Moreover, ARW policies are lightweight, easy to implement, and incur negligible storage and runtime overhead.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

Zhang¹,

Duan²,

Yang³

et al. 2017

IEICE Trans. Inf. & Syst.

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“…The authors of CCF-LRU (Li & Jin, 2009) further refine the idea of LRUWSR by distinguishing between cold-clean and hot-clean pages. Cold pages are distinguished from hot pages using the Second Chance algorithm.…”

Section: Related Workmentioning

confidence: 99%

Flash-Aware Buffer Management for Database Systems

Jin

Härder

2013

International Journal of Knowledge-Based Organizations

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Classical buffer replacement policies, e. g., LRU, are suboptimal for database systems having flash disks for persistence, because they are not aware of the distinguished characteristics of flash-based storage devices. We introduce the basic principles of buffer management for such devices and present two efficient buffer algorithms that apply these principles. These algorithms significantly improve the performance of flash-based databases, as confirmed by our trace-driven performance study.

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ECR: Eviction‐cost‐aware cache management policy for page‐level flash‐based SSDs

Chen

2019

Concurrency and Computation

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Summary Cache management policy plays a key role in offering low latency access to flash‐based SSDs. Most existing solutions including LRU and its successors only focus on improving the cache hit ratio, but rarely consider to reduce the waiting time of the eviction operation in the page‐level mapping FTLs. As the workloads spreading across internal chips of modern flash‐based SSDs are often highly imbalanced when workloads are write‐intensive, the time cost of evicting a dirty page from cache varies in a wide range. In this paper, we propose a novel eviction‐cost‐aware cache management policy, called ECR, to minimize the eviction cost in write‐dominant applications. ECR gives a higher probability to evict a page, which causes the shortest waiting time in the corresponding chip queue. To achieve this, we introduce a monitor module to keep track of states of all chip queues, and a multi‐LRU list structure to accelerate the selection of a victim chip and a target page in cache to perform an eviction. Our experimental results show that ECR can significantly reduce the average response time by as much as 59.55% and 44.84% compared to LRU and GCaR‐CFLRU, respectively, where GCaR‐CFLRU is the combination of state‐of‐the‐art algorithm GCaR and CFLRU.

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CCF-LRU: a new buffer replacement algorithm for flash memory

Cited by 103 publications

References 8 publications

ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

Flash-Aware Buffer Management for Database Systems

ECR: Eviction‐cost‐aware cache management policy for page‐level flash‐based SSDs

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