CEDR: A Compiler-integrated, Extensible DSSoC Runtime

Mack, Joshua; Hassan, Sahil; Kumbhare, Nirmal; Gonzalez, Miguel Castro; Akoglu, Ali

doi:10.1145/3529257

Cited by 16 publications

(4 citation statements)

References 49 publications

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“…The full-system hardware that integrated the cores and accelerators was implemented on a Xilinx Zynq UltraScale+ ZCU102 FPGA [42]. Runtime Environment: This study utilized the CEDR runtime framework [5] to implement DAS and evaluate its benefits for a DSSoC. CEDR allows users to compile and execute applications on heterogeneous SoC architectures.…”

Section: Methodsmentioning

confidence: 99%

“…Details of the workload mixes are given in Appendix B. Emulation Environment: Conducting a realistic runtime overhead and energy analysis is one of our key goals in this study. For this purpose, we leverage a Compiler-integrated, Extensible DSSoC Runtime (CEDR) framework introduced by Mack et al [5]. The CEDR has been validated extensively on x86 and Arm-based platforms.…”

Section: Domain Applicationsmentioning

confidence: 99%

“…For example, a DSSoC for autonomous driving incorporates computer vision and deep learning accelerators, whereas a DSSoC for a 5G/6G communication domain accelerates signal processing operations such as a fast Fourier transform (FFT). In addition, general-purpose CPU clusters and programmable accelerators, such as coarse-grained reconfigurable architectures (CGRA), offer alternative execution paths for a broader set of tasks besides improving flexibility [2,5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Goksoy,

Hassan,

Krishnakumar

et al. 2023

JLPEA

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Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.

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Section: Methodsmentioning

confidence: 99%

Section: Domain Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Goksoy,

Hassan,

Krishnakumar

et al. 2023

JLPEA

View full text Add to dashboard Cite

show abstract

“…• Ensuring End-User Compatibility: PEs in DS-IMCs should expose applications programming interfaces (APIs) that allow existing applications to execute with minimal modifications [121]. Runtime frameworks play a crucial role, using application source code and stateof-the-art resource management techniques [122].…”

Section: ) Software Developmentmentioning

confidence: 99%

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

Yusuf,

Adegbija,

Gajaria

2024

IEEE Access

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In recent years, the rapid growth of big data and the increasing demand for high-performance computing have fueled the development of novel computing architectures. Among these, in-memory computing architectures that leverage the high-density and low-latency nature of modern memory technologies have emerged as promising solutions for domain-specific computing applications. STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) is one such in-memory computing technology that holds great potential for this field due to its non-volatility, high endurance, and low power consumption. In this survey paper, we aim to provide a comprehensive overview of the state-of-the-art in STT-MRAM-based domainspecific in-memory computing (DS-IMC) architectures. We examine the challenges, opportunities, and trade-offs associated with these architectures from the perspective of various application domains, like machine learning, image and signal processing, and data encryption. We explore different experimental research tools used in studying these architectures, guidelines for efficiently designing them, and gaps in the state-of-the-art that necessitate future research and development.INDEX TERMS domain-specific architectures, in-memory computing, spin-transfer torque RAM.

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Deep Reinforcement Learning for System-on-Chip: Myths and Realities

Sung

Ryu

2022

IEEE Access

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CEDR: A Compiler-integrated, Extensible DSSoC Runtime

Cited by 16 publications

References 49 publications

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

Deep Reinforcement Learning for System-on-Chip: Myths and Realities

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