Cell Operation Technologies to Overcome Scale-down Issues in 3D NAND Flash Memory

Kim, Wandong; Byeon, Dae–Seok; Joe, Sung-Min; Lee, Jin-Yub; Song, Jay Hyok

doi:10.1109/iceic54506.2022.9748545

Cited by 5 publications

(4 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, high aspect-ratio hole etching reduces the hole radius toward the lower WL and strengthens the electric field applied to the gate dielectric [57]. This increases the program speed of the lower WL, but further deteriorates WL-to-WL interference when the aggressor cell becomes the lower WL [58]. To improve this phenomenon, instead of programming from lower WL to upper WL, performing programming from upper WL to lower WL can greatly relieve the cell-to-cell interference between WLs [59].…”

Section: Cell Variation Improvementmentioning

confidence: 99%

See 1 more Smart Citation

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

View full text Add to dashboard Cite

The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

show abstract

Section: Cell Variation Improvementmentioning

confidence: 99%

“…To improve the above problem, W. Kim et al proposed a read level adjustment method according to WLn + 1 Pattern [58], as shown in Figure 11. First, to broadly classify WLn + 1 pattern into two types, a pre-sensing operation is performed on WLn + 1.…”

Section: The Wl Pitch Scalingmentioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

View full text Add to dashboard Cite

show abstract

“…Although 3D process technology successfully enabled us to break through the scalingdown limit of conventional 2D planar NAND flash memory, 3D VNAND flash memory has encountered new challenges due to its unique 3D architecture and new flash cell structure [10][11][12][13][14][15][16][17][18][19]. For example, due to the three-dimensional (like cubic structure) block…”

Section: Introductionmentioning

confidence: 99%

“…The 2D planar NAND flash memory stores charges in a conductor called the floating gate, whereas the 3D VNAND flash memory stores bit information in a non-conductive (i.e., dielectric) layer within a CT-type cell called the SiN trap layer. The different cell structure of 3D VNAND flash memory causes new reliability issues such as early charge loss [15,17,18] or lateral charge spreading [13,14,19], which did not need to be considered in 2D planar NAND flash memory (more details are described in Section 2).…”

Section: Introductionmentioning

confidence: 99%

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Kim,

Seo,

Kim

2024

Eng

View full text Add to dashboard Cite

In order to successfully achieve mass production in NAND flash memory, a novel test procedure has been proposed to electrically detect and screen the channel hole defects, such as Not-Open, Bowing, and Bending, which are unique in high-density 3D NAND flash memory. Since channel hole defects lead to catastrophic failure (i.e., malfunction of basic NAND operations), detecting and screening defects in advance is one of the key challenges of guaranteeing the quality of flash products in the NAND manufacturing process. Based on analysis of the physical and electrical mechanisms of the channel hole defect, we have developed a two-step test procedure that consists of pattern-based and stress-based screen methodologies. By optimizing test patterns depending on the type of defect, the pattern-based screen is effective for detecting the type of Hard channel hole defects. The stress-based screen is carefully implemented to detect hidden Soft channel hole defects without degrading the reliability of NAND flash memory. In addition, we have attempted to further optimize the current version of our technique to minimize test time overhead, thus enabling 72.2% improvement in total test time. Experimental results using real 160 3D NAND flash chips show that our technique can efficiently detect and screen out various types of channel hole defects with minimum test time and negligible degradation in the flash reliability.

show abstract