Cell replication and redundancy elimination during placement for cycle time optimization

Neumann, Ingmar; Stoffel, Dominik; Hartje, Hendrik; Kunz, Wolfgang

doi:10.1109/iccad.1999.810614

Cited by 9 publications

(6 citation statements)

References 10 publications

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“…Neumann et al [11] apply logic duplication in a recursive partitioning-based timing-driven placement flow. During each recursion, they perform timing analysis, net length estimation and weight calculation, bipartitioning and cell replication sequentially.…”

Section: Figure 3 Impact Of Duplication On Placementmentioning

confidence: 99%

Simultaneous timing-driven placement and duplication

Chen¹,

Cong

2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

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Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to minimize the longest path delay. We introduce the notion of feasible region and super feasible region to improve the critical path monotonicity from a global perspective. We introduce a constrained gain graph to perform optimal incremental legalization under complex constraints. We also formulate a timing-constrained global redundancy removal problem and propose a heuristic solution. Our SPD algorithm outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 27% in longest path estimate delay and 18% in routed delay. The increase in overall runtime is less than 2% and the increase in area is less than 1%.

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Section: Figure 3 Impact Of Duplication On Placementmentioning

confidence: 99%

Simultaneous timing-driven placement and duplication

Chen¹,

Cong

2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

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“…Neumann et al [1999] apply logic duplication in a recursive partitioning-based timing-driven placement flow. During each recursion, they sequentially perform timing analysis, net length estimation and weight calculation, bipartitioning, and cell replication.…”

Section: Review Of Existing Workmentioning

confidence: 99%

Simultaneous placement with clustering and duplication

Chen¹,

Cong

2004

ACM Trans. Des. Autom. Electron. Syst.

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Clustering, duplication, and placement are critical steps in a cluster-based FPGA design flow. Clustering has a great impact on the wirelength, timing, and routability of a circuit. Logic duplication is an effective method for improving performance while maintaining the logic equivalence of a circuit. Based on several novel algorithmic contributions, we present an efficient and effective algorithm named SPCD (simultaneous placement with clustering and duplication) which performs clustering and duplication during placement for wirelength and timing minimization. First, we incorporate a path counting-based net weighting scheme for more effective timing optimization. Secondly, we introduce a novel method of moving a fragment of a cluster (called a fragment level move) during placement to optimize the clustering structure. To reduce the critical path detour during legalization from a more global perspective, we also introduce the notions of a monotone region and a global monotone region in which improvement to the local/global path detour is guaranteed. Furthermore, we introduce a notion of a constrained gain graph to embed all complex FPGA clustering constraints, and implement an optimal incremental legalization algorithm under such constraints. Finally, in order to reduce the circuit area, we formulate a timing-constrained global redundancy removal problem and propose a heuristic solution. Our SPCD algorithm outperforms a widely used academic FPGA placement flow, T-VPack + VPR, with an average reduction of 31% in the longest path estimate delay and 18% in the routed delay. We also apply our SPCD algorithm to Altera's Stratix architecture in a commercial FPGA implementation flow (Quartus II 4.0). The routed result achieved by our SPCD algorithm outperforms VPR by 20% and outperforms Quartus II 4.0 by 4%.

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“…However, applicability of this strategy in reducing the circuit delay has not been studied in detail. One of the few works is [12], which addresses the gate duplication problem in a performance driven perspective. It integrates cell replication into a layout driven framework.…”

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confidence: 99%

Timing driven gate duplication

Srivastava

Kastner

Chen

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.

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Cell replication and redundancy elimination during placement for cycle time optimization

Abstract: This paper presents a new timing driven approach for cell

Cited by 9 publications

References 10 publications

Simultaneous timing-driven placement and duplication

Simultaneous timing-driven placement and duplication

Simultaneous placement with clustering and duplication

Timing driven gate duplication

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