CellMT: A cooperative multithreading library for the Cell/B.E.

Beltrán, Vicenç; Carrera, David; Torres, Jordi; Ayguadé, Eduard

doi:10.1109/hipc.2009.5433205

Cited by 10 publications

(7 citation statements)

References 10 publications

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“…Some other work like [Beltran et al 2009] and [Ahmed et al 2008] address the problem of overlapping computations and data transfers by using multithreading so that the context switch occurs at the request of data not available in local store. This technique can be more efficient than a double or multi-buffering technique for applications with less regular computation and data access patterns.…”

Section: Convolutionmentioning

confidence: 99%

Optimizing explicit data transfers for data parallel applications on the cell architecture

Saidi

Tendulkar

Lepley

et al. 2012

ACM Trans. Archit. Code Optim.

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In this paper we investigate a general approach to automate some deployment decisions for a certain class of applications on multi-core computers. We consider data-parallelizable programs that use the well-known double buffering technique to bring the data from the off-chip slow memory to the local memory of the cores via a DMA (direct memory access) mechanism. Based on the computation time and size of elementary data items as well as DMA characteristics, we derive optimal and near optimal values for the number of blocks that should be clustered in a single DMA command. We then extend the results to the case where a computation for one data item needs some data in its neighborhood. In this setting we characterize the performance of several alternative mechanisms for data sharing. Our models are validated experimentally using a cycle-accurate simulator of the Cell Broadband Engine architecture.

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Section: Convolutionmentioning

confidence: 99%

Optimizing explicit data transfers for data parallel applications on the cell architecture

Saidi

Tendulkar

Lepley

et al. 2012

ACM Trans. Archit. Code Optim.

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“…To support communication-computation overlap, CellMP uses CellMT threads. 11,12 Usually, two SPU threads are created in each SPU, so that while one of them is computing, the other is in the data-transfer stage.…”

Section: Cellmpmentioning

confidence: 99%

Parallel Programming Models for Heterogeneous Multicore Architectures

Ferrer

Bellens²,

Beltrán

et al. 2010

IEEE Micro

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“…Prior solutions can be categorized into solutions that delegate data caching to programmers through a simplified API which hides the details of prefetching [6], [7], [30], solutions that semi-automate caching and prefetching by leveraging data annotations provided by programmers [10], [11], [12], [13], and solutions that hide all details of caching and prefetching from programmers, presenting them instead with a high-level programming API, such as OpenMP [14], [15], [16], [17].…”

Section: Related Workmentioning

confidence: 99%

“…Library frameworks that delegate software caching and prefetching to programmers such as IBM's ALF [7], RapidMind [6], and CellMT [30] provide APIs to express contiguous (unit-stride) and non-contiguous (non-unit-stride) data transfers to and from parallel tasks executing on heterogeneous cores. The implementation of these data transfers is hidden in the respective runtime libraries.…”

Section: Related Workmentioning

confidence: 99%

Strider: Runtime Support for Optimizing Strided Data Accesses on Multi-Cores with Explicitly Managed Memories

Yeom

Nikolopoulos²

2010

2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-Multi-core processors with explicitly-managed local memories provide advanced capabilities to optimize data caching and prefetching in software. Unfortunately, these capabilities are neither easily accessible to programmers, nor exploited to their maximum potential by current language, compiler, or runtime frameworks. We present Strider, a runtime framework for optimizing compilers on multi-core processors with softwaremanaged memories. Strider transparently optimizes grouping, decomposition, and scheduling of explicit software-managed accesses to multi-dimensional arrays in nested loops, given a highlevel specification of loops and their data access patterns. In particular, Strider contributes new methods to improve temporal locality, optimize the critical path of scheduling data transfers for multi-stride accesses in regular nested parallel loops, and distribute accesses between cores. The prototype of Strider on the IBM Cell processor performs competitively to hand-optimized code and better than contemporary language frameworks, in both non-trivial parallel applications and important application kernels.

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CellMT: A cooperative multithreading library for the Cell/B.E.

Abstract: The Cell BE processor

Cited by 10 publications

References 10 publications

Optimizing explicit data transfers for data parallel applications on the cell architecture

Optimizing explicit data transfers for data parallel applications on the cell architecture

Parallel Programming Models for Heterogeneous Multicore Architectures

Strider: Runtime Support for Optimizing Strided Data Accesses on Multi-Cores with Explicitly Managed Memories

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