Center wordline cell: A new symmetric layout cell for 64 Mb SRAM

Abstract

A new symmetric memory cell, in which one wordline is placed at the center, has been developed for 64Mb SRAM. This new center wordline cell has the benefits of a small cell size, good stability with operation voltages as low as 1.7V, and suitability for implementation of phase shift lithography. A high performance TFT; which has on/off ratio of 7 orders even at 2.5V operation, is mounted in this cell. IntmductionAs supply voltages decrease in accordance with the reduction in device dimensions, memory cell stability during read/write operations is becoming an increasingly important issue in the development of high density SRAMs. For 16Mb SRAMs, symmetric split wordline cell shown in Fig. l(a) was proposed to prevent the degradation of cell stability caused by cell unbalance in substitution for the asymmetric cell layout, shown in Fig. l(b), which was widely used inIn the split wordline cell, however, cell size reduction is difficult because each cell has two wordlines. Furthermore, this cell requires a very tight bitline pitch which causes a serious problem with aluminum bitline reliability issues and limits high speed operation because of the increased bitline capacitance. A single bitline SRAM architecture was proposed to solve these problems [3]. However, this architecture needs rather complicated read/write operation, and must pay a penalty in high speed operation.In this paper, we propose a new symmetric layout cell suitable for 64Mb SRAM and show that this cell has superior stability under low voltage operation. Fig. 2 shows the newly developed center wordline cell. This cell has a symmetric layout and the driver transistors are positioned on either side of the wordline which is located in the center of the cell. By saving the space of the additional wordline, a cell size of 3.3(1.5x2.2)pm2 has been achieved using 0.25pn design rules. This cell is 10% smaller and has a bitline pitch of 0.75pm, which is 15% looser, than a split wordline cell using comparable design rules. Fig. 2(b),(c) shows the layout of the TFT and capacitors. Fig. 3 illustrates the cross sectional view of the center wordline cell. Second polysilicon is used for cross interconnection of the cell flip-flops and also used for the gate electrode of the load TlTs. Channel polysilicon of the TlT and VCC lines are formed with third polysilicon. Fourth polysilicon and fifth polysilicon, which also is a ground plate, form a capacitor to improve soft error immunity. The layer assignment of the cell structure is summarized in Table 1. 64K-4Mb S U M S [1,2]. Cell design Fabrication processIn order to realize a small cell size, the following technologies were used.First, a buried diffusion layer was formed under the gate electrode to connect the access transistor and bit contact. Arsenic was implanted in this layer prior to gate oxidation.Second, polysilicon side contact was adopted as shown in Fig. 3. The contact hole was opened through the third and second polysilicon, and the n+ polysilicon plug, which was filled in the contact hole, connected the f...