CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Abstract

This paper explores and evaluates 6-transistor static random-access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Åm-compatible (A5) and 3-Åm-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked devices as compared to 14-Åmcompatible (A14) nanosheet technology and 10-Åm-compatible (A10) forksheet technology counterparts, respectively. Dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. Aggressive area scaling however introduces routing complexity and limits the node-to-node power and performance gain. The interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

Design and exploration of vertically stacked complementary tunneling field-effect transistors

“…4) Hence, this design is endorsed for sub-3 nm technology nodes and beyond (Angstrom (A 0 ) nodes). 5,6) The benefit of the FP is most advantageous for digital circuit designs, e.g. inverters, static random-access memory (SRAM), and so on.…”

“…As stated earlier, the analysis of D pn is crucial for sequential CFET/CTFET design options to reduce the parasitics. 6,8,14,19) Here, the significance of D pn is investigated with physical and DC behavior in n-and p-CTFETs at suitable biasing conditions (see Fig. 3).…”