Chai-Tea, Cryptographic Hardware Implementations of xTEA

Kaps, Jens-Peter

doi:10.1007/978-3-540-89754-5_28

Cited by 86 publications

(39 citation statements)

References 23 publications

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“…They are Advanced Encryption Standard (AES) [4][5][6][7], Data Encryption Standard (DES) [8], Tiny Encryption Algorithm (TEA) [9,10], and Extended TEA (XTEA) [11]. These encryption algorithms are not suited to be implemented in a resource constrained system due to various complexities involved like i.e.…”

Section: Related Workmentioning

confidence: 99%

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Efficient Modular Adders for Scalable Encryption Algorithm

Kumar¹,

Kesava²,

Salivahanan³

2011

IJCA

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SEA -Scalable Encryption Algorithm is a block cipher based symmetric encryption scheme, specially designed for resource constrained devices. SEA proposes low computational encryption routines (i.e. less code size, memory and power) for processors with a restricted instruction set. SEA is parametric with plain-text, key and microprocessor size, and meant for efficient combination of encryption/decryption and key derivation. The performance of modified SEA using efficient architectures of 2 b and 2 b -1 modular adders in a Field programmable gate array (FPGA) device is investigated. In this paper, an iterative based loop design of the block cipher is first implemented on FPGA. The proposed modular adders in SEA achieve lower area and power consumption on the target platform VIRTEX-4, xc4vl25-10ff668. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding.

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Section: Related Workmentioning

confidence: 99%

“…So in terms of security TEA is insecure. XTEA [11] was an advanced version of TEA, mainly aimed at improving all the security glitches. XTEA has complex key scheduling and rearrangement of Shift XOR and addition operations.…”

Section: Related Workmentioning

confidence: 99%

Efficient Modular Adders for Scalable Encryption Algorithm

Kumar¹,

Kesava²,

Salivahanan³

2011

IJCA

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“…Following these studies, a significant number of research investigations appeared emphasizing different techniques for hardware implementation. Some studies focused on software rather than hardware implementations of TEA and XTEA algorithms, such as [6]- [12]. A few major efforts have studied both hardware and software aspects of TEA for cost effective use of RFID applications [13] [14] [15] [16].…”

Section: Introductionmentioning

confidence: 99%

“…In [6] the author studied XTEA implementation on both the ASIC and FPGA programmable logic platforms. The FPGA implementation used Xilinx ISE 9.1 tools with Xilinx Virtex 5 and Spartan 3 FPGAs, containing the XC3S50-5 and XC3S200-5 FPGA devices, respectively, and reached a real-time encryption throughput rate of 36 Mb/s.…”

Section: Introductionmentioning

confidence: 99%

Programmable SoC for an XTEA Encryption Algorithm Using a Co-Design Environment Replication Performance Approach

Meer¹

2017

JCC

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With the rapid development of wired and wireless networks, the security needs within network systems are becoming increasingly intensive owing to the continuous development of new applications. Existing cryptography algorithms differ from each other in many ways including their security complexity, size of the key and words operated on, and processing time. Nevertheless, the main factors that prioritize an encryption algorithm over others are its ability to secure and protect data against attacks and its speed and efficiency. In this study, a reconfigurable Co-Design multi-purpose security design with very low complexity, weight, and cost, has been developed using Extended Tiny Encryption Algorithm (XTEA) data encryption standards. The paper aims to discuss issues and present solutions associated with this system, as well as compare the Co-Design implementation approach with Full-Hardware and Full-Software solutions. The main contribution that this paper offers is the profiling of XTEA cryptographic algorithm to reach more satisfactory understanding of its computation structure that leads to fully software, fully hardware, beside the co-design implementations all together, of this light weight encryption algorithm.

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“…Early work focuses on optimizing hardware implementations of standardized block ciphers such as AES [16], IDEA [25] and XTEA [22]. Later on, researchers have shown how to modify a classical block cipher like DES [24] for lightweight applications.…”

Section: Introductionmentioning

confidence: 99%

WG-8: A Lightweight Stream Cipher for Resource-Constrained Smart Devices

Fan

Mandal

Gong

2013

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Abstract. Lightweight cryptographic primitives are essential for securing pervasive embedded devices like RFID tags, smart cards, and wireless sensor nodes. In this paper, we present a lightweight stream cipher WG-8, which is tailored from the well-known Welch-Gong (WG) stream cipher family, for resource-constrained devices. WG-8 inherits the good randomness and cryptographic properties of the WG stream cipher family and is resistant to the most common attacks against stream ciphers. The software implementations of the WG-8 stream cipher on two popular lowpower microcontrollers as well as the extensive comparison with other lightweight cryptography implementations highlight that in the context of securing lightweight embedded applications WG-8 has favorable performance and low energy consumption.

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Chai-Tea, Cryptographic Hardware Implementations of xTEA

Cited by 86 publications

References 23 publications

Efficient Modular Adders for Scalable Encryption Algorithm

Efficient Modular Adders for Scalable Encryption Algorithm

Programmable SoC for an XTEA Encryption Algorithm Using a Co-Design Environment Replication Performance Approach

WG-8: A Lightweight Stream Cipher for Resource-Constrained Smart Devices

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