Chaining of hardware accelerated Virtual Network Functions in PCIe Environments

Abstract

The growth of compute-intensive applications causes an increasing demand for computing resources in both data centers and underlying networks. To satisfy these computing and networking demands, hardware-accelerated computing with GPUs and FPGAs becomes more and more prevalent. However, current approaches of accelerated Virtual Network Functions (VNF), typically based on PCIe accelerator cards, suffer from many superfluous data transfers between the memory of hosts and accelerator devices.In this work we propose "host bypassing" for chained hardware-accelerated network functions, which reduces memory copying to a minimum, which increases throughput and reduces latency.

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DoubleDeck: Decoupling Complex Control Logic of Network Protocols to Facilitate Efficient Hardware Implementation

“…Traditional software-based protocols have difficulties meeting high-performance processing requirements due to problems such as poor processing performance and high processing latency [9,10]. For this reason, some recent studies [11][12][13][14] were proposed to improve the processing performance of the protocol by using hardware implementation protocols (i.e., FPGA, NP, and GPU).…”