Challenges and directions for testing IC

Ali, Liakot; Sidek, Roslina Mohd; Aris, Ishak; Suparjo, B.S.; Ali, Mohd

doi:10.1016/j.vlsi.2003.09.006

Cited by 19 publications

(7 citation statements)

References 51 publications

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“…Roadmaps for semiconductors showing increasing complexity, and dramatically increasing test challenges and requirements, are summarized by [5] within a roadmap which sets semiconductor technology benefits in context with measurement and testing. Nevertheless, as outlined above, in the overview about the evolution of semiconductor test, various new methods design for test (DFT), built-in self-test (BIST) are developed to ease and, at the same time, to increase testability.…”

Section: Roadmaps For Semiconductors and Testmentioning

confidence: 99%

Challenges for Semiconductor Test Engineering: A Review Paper

et al. 2012

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Today's economical cycles challenge the test program generation process for semiconductors with regard to productivity, time-to-market, increasing quality requirements and manufacturing robustness, while, at the same time, the complexity of the system-on-a-chip mixed-signal integrated circuits to be tested increases significantly. Furthermore, commercial challenges in combination with competitive advantage become an important factor, not only within semiconductor manufacturing, but also within test program development. This paper provides a review of these challenges, and how they might be addressed. We first give a short introduction and background on semiconductor testing and test development with the focus on mixed-signal and systems-on-chip. This is followed by current roadmaps and considerations for test program software development. Based on the highlighted strength and weaknesses of the reviewed approaches, the authors conclude with some recommendations to address these challenges by adopting software engineering methods for the test program development process.

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Section: Roadmaps For Semiconductors and Testmentioning

confidence: 99%

Challenges for Semiconductor Test Engineering: A Review Paper

et al. 2012

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“…In today’s world, for many emerging and demanding applications where security and reliability are an issue, ASIC implementation of AES cryptoprocessor is the best solution for the clients. However, for designing ASIC or any complex chip, Design for Testability (DFT) is a prime concern because testing a VLSI chip using Automatic Test Equipment (ATE) is highly complex, time-consuming as well as expensive [ 23 , 24 ]. To deal with the testing problem at the chip level, incorporating Built-in Self-Test (BIST) capability inside a chip is a widely accepted approach [ 25 – 30 ] and it is a norm of this day in the VLSI industry.…”

Section: Introductionmentioning

confidence: 99%

Design of a BIST implemented AES crypto-processor ASIC

2021

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This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

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“…In this, a set of pseudo-random test patterns is generated randomly from 2 q possible input patterns where q is the primary input number of the circuit. The disadvantage of this approach is that the testing length is probabily very large [3] to achieve an adequate fault coverage since the CUT may contain hard-to-detect faults, also called random-pattern-resistant faults, which have low detection probabilities and therefore limit the fault coverage that can be obtained with pseudo-random patterns [4]. A possible solution to the aforementioned problem is to applying reseeding technique for LFSR-based TPGs.…”

Section: Introductionmentioning

confidence: 99%

BMA-based reseeding technique

Souza

Soares

Costa

et al. 2012

2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings

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This paper presents a new scheme of Linear-Feedback Shift-Register (LFSR) reseeding technique based on Berlekamp-Massey Algorithm (BMA). It is proposed an LFSRbased TPG which its feedback polynomial is programmable by a BMA-synthesized LFSR that, in its turn, generates speci c patterns to change the LFSR-based TPG's feedback polynomial. Using the proposed method, high fault coverage is achieved with a small number of test patterns. Experimental results have been shown the effectively of the proposed method.

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Challenges and directions for testing IC

Cited by 19 publications

References 51 publications

Challenges for Semiconductor Test Engineering: A Review Paper

Challenges for Semiconductor Test Engineering: A Review Paper

Design of a BIST implemented AES crypto-processor ASIC

BMA-based reseeding technique

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