Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen,

doi:10.1109/date.2012.6176689

Cited by 45 publications

(24 citation statements)

References 39 publications

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“…Despite many challenges, the three-dimensional integrated circuit (3D IC) is a hot topic in semiconductor industry these days [2], [6], [8]. To achieve higher levels of integration, multiple layers of active electronic component are stacked vertically in a 3D IC.…”

Section: Introductionmentioning

confidence: 99%

Yield analysis of a novel wafer manipulation method in 3D stacking

Zhang

Agrawal

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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Abstract-Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC, including heterogeneous integration, reduced delay and power dissipation, smaller chip area, etc. Wafer-on-wafer stacking is attractive for 3D IC fabrication, but it suffers from low compound yield of the stacked chips. To improve the compound yield, a novel manipulation of sector symmetry and cut (SSC) is proposed. In this method, wafers with rotational symmetry are cut into identical sectors, which are then used to replenish the repositories. The SSC method is combined with best-pair matching algorithm for compound yield evaluation. Simulation results show that: 1) For wafers with radially clustered defects, plain rotation of wafers offers trivial benefits in yield. 2) SSC shows significantly higher yield than that for existing methods under various conditions. The advantage becomes even more obvious with increased repository size, larger number of stacked layers, and the decreased wafer yield. 3) A cut number of 4 is always optimal in increasing the final production size of good 3D ICs.

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Section: Introductionmentioning

confidence: 99%

Yield analysis of a novel wafer manipulation method in 3D stacking

Zhang

Agrawal

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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“…Test challenges for 3D-SICs are discussed in [Marinissen12a,Noia11]. The need for standards like IEEE P1838 is discussed.…”

Section: Related Work 29mentioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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“…Solutions include contactless test [109] or inserting additional probing pads to non-bottom dies at the cost of increased area [110]. Another concern is whether to perform the test before or after wafer thinning [111]. Running tests before wafer thinning excludes defects due to thinning.…”

Section: Pre-bond Testingmentioning

confidence: 99%

“…Final testing, on the other hand, is the last quality screening step prior to shipping the product to customers; any part of the 3D chip should remain testable here [111].…”

Section: Mid-bond Post-bond and Final Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Cited by 45 publications

References 39 publications

Yield analysis of a novel wafer manipulation method in 3D stacking

Yield analysis of a novel wafer manipulation method in 3D stacking

Thermal Issues in Testing of Advanced Systems on Chip

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

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