Challenges and solutions for 14nm FinFET etching

Huang, Jun; Li, Quanbo; Chong, Ermin; Chun-yan, YI; Li, Runling; Chenguang, Gai; Zhibiao, Ma; Zhang, Yu; Pang, Albert

doi:10.1109/cstic.2015.7153391

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…Conventional etching methods may lead to the inconsistent height of fins due to the significant etching micro-loading effect, which is also called the reactive ion etching (RIE) lag effect, as shown in Fig. 6 [18] . D 1 , D 2 and D 3 are the etching depths under the same etching condition and different opening pattern sizes.…”

Section: Alementioning

confidence: 99%

Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.

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Section: Alementioning

confidence: 99%

Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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show abstract

“…Bias pulsing improve intra-cell depth loading (a) loading without pulsing and (b) loading with pulsing. Reproduced with permission from [121]. Copyright IEEE, 2015.…”

Section: Depth Loading Control Of Fin Etchingmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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Challenges and solutions for 14nm FinFET etching

Cited by 2 publications

References 3 publications

Advanced process and electron device technology

Advanced process and electron device technology

The Challenges of Advanced CMOS Process from 2D to 3D

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