Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Abstract

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.IEDM09-290 12.1.2

Assessing Benefits of a Buried Interconnect Layer in Digital Designs

“…A cartoon diagram of source/drain contacts through V -1 is shown in Figure 3. With FinFET devices, the source/drain region is usually formed by merging fins by epitaxial growth of SiGe [15]. Therefore, the buried vias do not need to contact the thin fins directly (which would have been very hard to control due to the overlay error).…”

Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

“…The aspect ratio of fin height over fin width is 25/10-nm due to limited fin pitch [10]. The FinFET channel is low-doped and the source/drain are doped with a maximum doping of 3×10 20 cm -3 .…”

“…Although the lifetime of 193nm immersion lithography has been extended by using double patterning technology, achieving tight control on CD variation at the nanometer scale, it still presents a significant challenge [10]. Simultaneously unavoidable statistical variability exists in nanometer scale transistors, which derives from the discreteness of charge and granularity of matter arising from sources of statistical variability such as random discrete dopants (RDD), gate and fin line-edge-roughness (GER and FER), metal gate granularity (MGG) (Fig.1).…”

Interplay between quantum mechanical effects and a discrete trap position in ultra-scaled FinFETs

“…However, even though the multi-gate transistors provide superior options for scalability, they also suffer from negative effects of various sources of variability [2][3][4]. For example, interface traps represent a non-negligible source of variability in ultra-scaled low-doped channel devices, such as FinFETs [4][5][6].…”