Challenges in clockgating for a low power ASIC methodology

Garrett, David; Stan, Mircea R.; Dean, A.

doi:10.1145/313817.313913

Cited by 25 publications

(9 citation statements)

References 15 publications

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“…A gated clock tree synthesis algorithm like that presented in [8][9][10][11] should be sufficient. For simplicity, we assume that we have a clock control logic unit synthesized based on flip-flops activity patterns for generating clock gating signals.…”

Section: Synthesis Of Delay-matching Gated Clock Treementioning

confidence: 99%

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Clock gating optimization with delay-matching

Hsu

Lin

2011

2011 Design, Automation &Amp; Test in Europe

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Clock gating is an effective method of reducing power dissipation of a high-performance circuit. However, deployment of gated cells increases the difficulty of optimizing a clock tree. In this paper, we propose a delay-matching approach to addressing this problem. Delay-matching uses gated cells whose timing characteristics are similar to that of their clock buffer (inverter) counterparts. It attains better slew and much smaller latency with comparable clock skew and less area when compared to type-matching. The skew of a delay-matching gated tree, just like the one generated by type-matching, is insensitive to process and operating corner variations. Besides, delay-matching ECO of a gated tree excels in preserving the original timing characteristics of the gated tree.

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Section: Synthesis Of Delay-matching Gated Clock Treementioning

confidence: 99%

“…Clock gating is an effective method of reducing power dissipation of a high-performance circuit [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Clock gating optimization with delay-matching

Hsu

Lin

2011

2011 Design, Automation &Amp; Test in Europe

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“…Previous researches on low power had established various approaches such as clock gating [13], buffer insertion and sizing [14], multi-voltage designs [15]. Among these approaches, clock gating used widely in high performance VLSI designs has been implanted to FPGA clock network.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of clock network for nanometer FPGA

Lai

2015

IEICE Electron. Express

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This paper is committed to design and implement FPGA clock network with overall considerations of speed and power in circuit design perspective. Mixed structure MUX, programmable delay adjustment unit and power-down bit strategies are presented to optimize its latency, skew and power. This clock network is implemented with 65 nm process and applied to own-designed FPGA. Test results indicate 21.7% reduction in latency and 54.5% reduction in skew, compared to counterpart FPGA device, while maintaining lower power consumption.

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“…Previous researches have presented a various approaches for optimizing power consumption, such as clock gating [1,2], buffer insertion [3,4], multi-supply voltage (MSV) designs [5], Globally Asynchronous Locally Synchronous (GALS) [6], and parallelism and pipeline [7]. Among these approaches, clock gating technique has been used widely in high performance VLSI design to reduce clock network power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, researches on clock gating have established a various approaches. [2] modified the traditional zero-skew clock tree pairing algorithms to include considerations of the clock gating groups and distribution. [8] presented a top-down methodology by splitting each fan-out region of clock gating cell to satisfy the setup time constraint.…”

Section: Introductionmentioning

confidence: 99%

Clock tree construction using gated clock cloning

Chen

Chang

Hung

et al. 2012

2012 4th Asia Symposium on Quality Electronic Design (ASQED)

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Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter γ that may be used to adjust the tradeoff between clock gating cell and buffer. The experimental results show that the number of clock gating cells and buffers reduced in each phase in our algorithm. Our solutions are better than greedy approach.

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Challenges in clockgating for a low power ASIC methodology

Abstract: Gating the clock is an important technique used in low

Cited by 25 publications

References 15 publications

Clock gating optimization with delay-matching

Clock gating optimization with delay-matching

Design and implementation of clock network for nanometer FPGA

Clock tree construction using gated clock cloning

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