“…Additional porosity can be introduced in the material, either through a sol-gel process or by inclusion of sacrifi cial nanoparticles (i.e., porogens), which are decomposed and desorbed during a high-temperature bake step. Introducing pores in a dielectric poses several challenges for successful integration into microelectronic circuits [17,18]. The mechanical strength of the dielectric is reduced by porosity, potentially leading to failure during chemical mechanical planarization (CMP) [19,20,21,22] or during wire bonding to the fi nished chip [23].…”