Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Wei, A.; Singh, Joginder; Bouche, G.; Zaleski, M.; Augur, Rod; Senapati, B.; Stephens, Jason; Lin, Irene Kong Cheh; Rashed, M.; Lei, Yuan; Kye, Jongwook; Woo, Youngtag; Zeng, Jia; Levinson, Harry; Wehbi, Ali; Hang, Peter; Ton-That, Van; Kanagala, Vijay; Yu, Donald; Blackwell, D. E.; Beece, Adam; Gao, Shan; Thangaraju, Sarasvathi; Alapati, Ramakanth; Samavedam, Srikanth

doi:10.1109/iedm.2014.7047076

Cited by 13 publications

(3 citation statements)

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“…Non-scalable pin size or pitch of solder bumps and balls imposes limitations on the bandwidth density of inter-chip I/O and will prevent power consumption per Gbps of wireline communication from scaling significantly. In [73] Global Foundries projects that the percentage of die area occupied by only analog I/O components would be between 40-60% in the 7 nm node. Therefore, it is expected that as technology scales and SOI processes develop the power-performance gap between wireless inter-chip interconnects and traditional wireline interconnects will continue to widen, pushing the advantage towards the wireless interconnections even more.…”

Section: Impact Of Technology Scaling On Inter-chip Wireless Interconmentioning

confidence: 99%

“…The high speed serial I/O channels are adopted from 65 nm designs and are shown to have a bandwidth of 15 Gbps with an energy consumption of 5 pJ/bit [108]. As analog I/O circuitry do not scale well with technology node these parameters are representative of current technology trends [73]. For the mm-wave wireless multi-chip system we have considered the inter-chip communication to utilize the mm-wave transceivers that are located at one of the central cores of each chip achieving a WI density of 1/16 WI/core.…”

Section: Comparison With Other Emerging Interconnect Technologiesmentioning

confidence: 99%

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The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Ganguly

Ahmed

Narde

et al. 2018

JLPEA

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With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

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Section: Impact Of Technology Scaling On Inter-chip Wireless Interconmentioning

confidence: 99%

Section: Comparison With Other Emerging Interconnect Technologiesmentioning

confidence: 99%

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Ganguly

Ahmed

Narde

et al. 2018

JLPEA

View full text Add to dashboard Cite

show abstract

“…Furthermore, the applications like Long-term evolution (LTE) phones and emerging sub-6GHz 5G bands demand transistors with better analog/Radiofrequency (RF) performance [3]. Therefore, the development of analog/RF capabilities in advanced FinFET technology nodes is essential to reap the System-on-Chip (SoC) benefits like low power and high performance in smaller area [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Bhoir

Chiarella

Ragnarsson

et al. 2019

IEEE J. Electron Devices Soc.

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This paper discusses in detail the effects of Sub-10nm fin-width (W fin ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm W fin regime, cannot be improved just by W fin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the W fin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

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Novel Stacked SiGe/Si FinFET Device with Subthreshold Swing of 68 mV/dec Using Optimized Thermal Budget and Channel Passivation Technology

Zhao

Zhang

et al. 2023

Silicon

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Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Cited by 13 publications

References 0 publications

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Novel Stacked SiGe/Si FinFET Device with Subthreshold Swing of 68 mV/dec Using Optimized Thermal Budget and Channel Passivation Technology

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