Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing

Abstract

Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

“…Dedicated hardware allows for the efficient execution of complex algorithms even in constrained contexts, where finding trade-offs among system aspects of interest, e.g. power consumption versus quality of service, may be fundamental [27]. Profiling the algorithms to find the sub-parts that can be accelerated is surely necessary, as well as the identification of parallelism, since parallel off-the-shelf or dedicated devices could improve both timing and power performance.…”

Efficient H.264 Decoder Architecture using External Memory and Pipelining

“…Table 1. The number of luma and chroma intra prediction unit comparison is depicted Design LUT FF luma [14] 545 127 luma [15] 212 37 luma [proposed] 83 284 chroma [14] 216 59 chroma [15] 163 33 chroma [proposed] 284 105…”

Optimized VLSI Architecture of HEVC Fractional Pixel Interpolators with Approximate Computing

“…In this regard, several works were proposed to cope with the strong limitations introduced by the I/O schemes and the Memory access Bandwidth on the algorithm's performance [4][5][6]. However, this work, like many others [7][8][9][10][11][12][13], focuses exclusively on the optimization of the computational kernel in order to maximize its throughput: Different works in the literature, including [14], show that a relevant portion of HEVC complexity is due to the motion estimation. Indeed, HEVC features a two-step motion compensation process, which first works on different search window sizes and then exploits an interpolation step for fractional pixel search refinement.…”

“…This second step relies on a separable 2D interpolation filter. In the last years several architectures for HEVC interpolation filters have been proposed in the literature, e.g., [7][8][9][10][11][12][13]. Most of the published architectures, including [7,[9][10][11][12], concentrate on the standard HEVC interpolation filters, hereinafter referred to as legacy filters.…”

“…Most of the published architectures, including [7,[9][10][11][12], concentrate on the standard HEVC interpolation filters, hereinafter referred to as legacy filters. However, the work in [15] showed that algorithmic-level approximate computing can be exploited to achieve energy efficiency in HEVC decoding and, to the best of our knowledge, [13] is the first paper showing an architecture for interpolation filters where energy/quality trade-offs can be exploited. In particular, in [13] multiply units are dynamically multiplexed, thus allowing to reduce the filter order at the runtime.…”