Challenging the Stateless Quo of Programmable Switches

Abstract

Programmable switches based on the Protocol Independent Switch Architecture (PISA) have greatly enhanced the flexibility of today's networks by allowing new packet protocols to be deployed without any hardware changes. They have also been instrumental in enabling a new computing paradigm in which parts of an application's logic run within the network core (in-network computing). The characteristics and requirements of in-network applications, however, are quite different from those of packet protocols for which programmable switches were originally designed. Packet protocols are typically stateless, while in-network applications require frequent operations on shared state maintained in the switch. This mismatch increases the developing complexity of in-network computing and hampers widespread adoption. In this paper, we describe the key obstacles to developing innetwork applications on PISA and propose rethinking the current switch architecture. Rather than changing the existing architecture, we propose augmenting it with a Stateful Data Plane (SDP). The SDP supports the requirements of stateful applications, while the conventional data plane (CDP) performs packet-protocol functions.

Flow-Aware Service Function Embedding Algorithm in Programmable Data Plane

“…Since the packets are processed by match-action tables in PDP instead of the software module on the CPU, the PDP switches can conduct only limited actions (e.g., count action, drop action, and modify header field action) [11]. Even though these actions are sufficient for simple networking operations (e.g., rewrite a packet header and select an output port) [15], these actions are not suited for more complex network operations of the stateful SFs [15], [16]. To address this problem, a new machine model called Banzai has been introduced [16].…”

“…Recently, programmable data planes (PDPs) have attracted considerable attention because of their easily reconfigurable data planes and line-rate packet processing performance. Moreover, PDP has also been instrumental in enabling a new computing paradigm in which parts of an application's logic run within the network core (i.e., in-network computing) [15]. This salient feature can mitigate the abovementioned limitations of softwarized SFs owing to its high performance and reconfiguration.…”

Ioi

“…This is 1000× faster than a CPU core! Although in-network inference with programmable switches has fundamental latency advantages over the conventional server-based solutions, each inference task requires intensive computation such as matrix multiplication, which is challenging in today's switches because of their limited resources [5,17]. Therefore, we propose a novel architecture called In-network Optical Inference (IOI) to leverages emerging optical matrix multiplication hardware [7] using commercially available modulators and photodetectors that already exist in today's transceivers.…”

The Nuts and Bolts of Building FlowLens

“…Figure 1 depicts the internals of a modern programmable switch, the Protocol Independent Switch Architecture (PISA) [12]. When a packet arrives at the switch's ingress interface, it is processed by a pipeline Constraints: To achieve line-rate at Tbps, PISA-like switches impose important constraints on the operations that MAU actions can do, requiring careful engineering when programming such devices effectively [16]. First, switching ASICs feature a small amount of stateful memory (≈100MB SRAM [24]), and only a fraction of the available SRAM can be used to allocate register arrays.…”