Chameleon: A workstation of a different colour

Heeb, Beat; Pfister, Cuno

doi:10.1007/3-540-57091-8_40

Cited by 18 publications

(3 citation statements)

References 2 publications

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“…The arithmetic functions and memory, features that are inefficient to implement in FPGAs and which are standard across most processors, are implemented efficiently in chips designed specifically for these applications. Other systems have adopted a similar approach, including another system intended for developing application-specific processors [Wolfe88], a workstation design with FPGAs for I/O functions and for coprocessor development [Heeb93], and a multiprocessor system with FPGA-based cache controllers for exploring different multiprocessor systems and caching policies [Öner95]. A somewhat related system is the CM-2X [Cuccaro93], a standard CM-2 supercomputer with the floating-point unit replaced with a Xilinx FPGA.…”

Section: Multi-fpga Systemsmentioning

confidence: 99%

The roles of FPGAs in reprogrammable systems

Hauck

1998

Proc. IEEE

278

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FPGA-based reprogrammable systems are revolutionizing some forms of computation and digital logic. As a logic emulation system they provide orders of magnitude speedup over software simulation. As a custom-computing machine they achieve the highest performance implementation for many types of applications. As a multi-mode system they yield significant hardware savings and provide truly generic hardware. In this paper we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems, as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.

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Section: Multi-fpga Systemsmentioning

confidence: 99%

The roles of FPGAs in reprogrammable systems

Hauck

1998

Proc. IEEE

278

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“…Besides our PAMs, which were built rst at IN-RIA in 1987 [4], then at DEC-PRL, other successful implementations of recongurable systems have been reported, in particular at the universi- ties of Edinburgh [5] and Zurich [6], and at the Supercomputer Research Center in Maryland [7]. The ENABLE machine is a system, built from FPGAs and SRAM, specically constructed at the university of Mannheim [8] for solving the TRT problem of section 3.2.…”

Section: Programmable Active Memoriesmentioning

confidence: 99%

Real-time high-energy physics applications on DECPeRLe-1 programmable active memory

Moll

Vuillemin

Boucard³

et al. 1996

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. The future Large Hadron Collider (LHC) to be built at CERN 1 , by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST 2 (RD-11) group and DEC-PRL PAM 3 team. We present implementations of the four foremost LHC algorithms on DECPeRLe-1 [1]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based machine built for just one of the algorithms [2]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

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“…Heeb and Pfister [5] also use FPGA's as reconfigurable accelerators to enhance the performance of a reducedinstruction set computer (RISC) processor in their system named Chameleon.…”

mentioning

confidence: 99%

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

Bosi¹,

Bois

Savaria

1999

IEEE Trans. VLSI Syst.

130

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In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal-and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides highlevel interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated, Dallas, TX. However, the proposed concept is not limited to a particular processor.Index Terms-Architectural tradeoffs, custom computing machine, design methodology, design reuse, DSP function library, hardware/software co-design, reconfigurable hardware accelerator.

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Chameleon: A workstation of a different colour

Cited by 18 publications

References 2 publications

The roles of FPGAs in reprogrammable systems

The roles of FPGAs in reprogrammable systems

Real-time high-energy physics applications on DECPeRLe-1 programmable active memory

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

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