Channel aware receiver front end for low power 2.4 GHz Wireless Sensor Network: A system level analysis

Zaini, Jennifer; Hameau, Frédéric; Taris, Thierry; Morche, Dominique; Tran, Le Quang Vinh; Audebert, P.

doi:10.1109/newcas.2016.7604741

Cited by 8 publications

(7 citation statements)

References 14 publications

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“…The probability distribution of the received power signal at the input of the receiver is plotted in Figure 6. The details of the calculation and the developed description of the channel conditions are presented in [10]. Figure 6 shows that the power of the incoming RF signal ranges from −90 dBm to −20 dBm.…”

Section: Probability Distribution Of the Received Powermentioning

confidence: 99%

“…The results of the computation for the proposed 3-modes receiver in terms of sensitivity ranges, percentages of the usage time in each mode and power consumptions are summed up in Table 2. 1 Calculation details available in [10].…”

Section: Optimized Reconfiguration Thresholdsmentioning

confidence: 99%

“…Probability distribution function (PDF) of the received power signal at the input of the receiver[10].…”

mentioning

confidence: 99%

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An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

Zaini-Desevedavy

Hameau

Taris

et al. 2018

JLPEA

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This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm 2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.

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Section: Probability Distribution Of the Received Powermentioning

confidence: 99%

Section: Optimized Reconfiguration Thresholdsmentioning

confidence: 99%

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An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

Zaini-Desevedavy

Hameau

Taris

et al. 2018

JLPEA

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“…More specifically, 60% of the power dedicated to the receiver (Rx) part of an RF module is consumed by the frequency synthesis and the RF amplification, thus compromising the node's lifetime [2]. To address this issue, a channel-aware solution is proposed in [3]. Based on the IEEE802.15.4 standard and a given scenario of WSN deployment, the probability distribution of the received power signal is derived in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…1. The lifetime of a node can be multiplied by a factor of 5 if the receiver front end (RFFE) features three modes of operation, with the specifications reported in Table I [3]. Focusing on the amplification stage, the investigations derive a set of specifications for the Low Noise Amplifier in each mode of operation.…”

Section: Introductionmentioning

confidence: 99%

Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications

et al. 2021

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This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350uW. It achieves a voltage gain (Gv) of 16.8dB and a noise figure (NF) of 6.6dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4dB and 5.4dB, the power consumption is 0.9mW. In the high-performance mode, the gain is maximum, 22.9dB, and the noise figure is minimum, 3.6dB, for a power consumption of 2mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to -16dBm. The reported LNA occupies only 0.0015mm 2 .

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Design of ULV ULP LNAs Exploiting FBB in FDSOI 28nm Technology

Aragones

Alvarez

Rovayo

et al. 2019

2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)

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Channel aware receiver front end for low power 2.4 GHz Wireless Sensor Network: A system level analysis

Cited by 8 publications

References 14 publications

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications

Design of ULV ULP LNAs Exploiting FBB in FDSOI 28nm Technology

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