Channel doping impact on FinFETs for 22nm and beyond

Lin, Chung-Hsun; Kambhampati, R.; Miller, Robert J.; Hook, T.B.; Bryant, A.; Haensch, Wilfried; Oldiges, P.; Lauer, Isaac; Yamashita, T.; Basker, V.; Standaert, T.; Rim, K.; Leobandung, E.; Bu, H.; Khare, Mukesh

doi:10.1109/vlsit.2012.6242438

Cited by 42 publications

(27 citation statements)

References 4 publications

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“…Since the constant current criteria is the most commonly used technique for V t definition 1 and has been conveniently used for measuring V t of huge number of transistors due to its simplicity, 17,18 the constant current criteria are appropriate for benchmarking of the V t variability with regard to the previously reported V t variability of FinFETs. 7,8,14,19,21,22 As clearly seen in Figs. 2 and 3, the TaSiN MG exhibits smaller V t fluctuation than the TiN MG does both for the long and short channel cases.…”

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confidence: 60%

“…As clearly seen, the TaSiN MG significantly suppresses the slope value in comparison to the TiN MG case and exhibits the A Vt value of 1.34 mV lm, which is the smallest one reported so far for MG-FinFETs. 7,8,14,19,21,22 Validity of the constant current criteria for the V t variability analysis is discussed as follows. We have previously confirmed that the V t variation measured by the constant current criteria is independent from the fluctuation of the parasitic resistance.…”

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confidence: 99%

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Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

Matsukawa

Liu

Mizubayashi

et al. 2013

Applied Physics Letters

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Articles you may be interested inStrain induced changes in the gate leakage current of n-channel metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 110, 014511 (2011); 10.1063/1.3603023 Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxidesemiconductor field-effect transistors with nitrogen and silicon incorporated HfO 2 gate dielectrics Appl. Phys. Lett. 98, 063504 (2011); 10.1063/1.3541879 Work function tuning of n -channel metal-oxide field-effect transistors using interfacial yttrium layer in fully silicided nickel gate Appl. Phys. Lett. 89, 233520 (2006); 10.1063/1.2402943 Physical and electrical properties of lanthanide-incorporated tantalum nitride for n -channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 87, 073506 (2005); 10.1063/1.1947901Polycrystalline silicon/metal stacked gate for threshold voltage control in metal-oxide-semiconductor field-effect transistors Appl.

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confidence: 60%

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confidence: 99%

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

Matsukawa

Liu

Mizubayashi

et al. 2013

Applied Physics Letters

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“…Ion implantation into metal gatestack of TiN/HfO2 provides suitable VT for devices keeping channel undopped. Another approach to achieve desired VT for device is by doping channel [15], which will definitely change A vt and hence corners of the device. Repeating SRAM device VT-targeting methodology with updated corners will result in desired WFs for gate-stack of SRAM devices.…”

Section: Methodology For Vt-targeting Using Work Function Tuningmentioning

confidence: 99%

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology highdensity (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546 μm 2 with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048 μm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1σ rsnm margin to retain the same yield in 10-nm-technology era.Index Terms-10-nm technology, design methodology, design technology co-optimization (DTCO), double patterning gate, FinFET SRAM design, high density (HD), selfaligned double patterning (SADP), self-aligned quadruple patterning (SAQP), SRAM threshold voltage (VT) targeting, technology SRAM.

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“…1. Cross-sectional TEM images of (a) a FinFET channel [7], (b) multi-finger FinFET arrays [8] under the gate along the fin-width direction.…”

Section: Trapezoidal Finfetmentioning

confidence: 99%

“…Additionally, it was revealed that the microscopic cross sections of the fin body of the transistor in the processor actually have a trapezoidal shape, as shown in Fig. 1 [6][7][8]. Although a FinFET is believed to have uniform thickness across the height of a fin, the trapezoidal cross section has been found to be markedly different from the idealized rectangular fin body in many studies [9].…”

Section: Introductionmentioning

confidence: 99%

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

Ryu¹,

Kim

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computeraided-design (TCAD) simulation shows that the onstate current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10° to 20° is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

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Channel doping impact on FinFETs for 22nm and beyond

Cited by 42 publications

References 4 publications

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

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