Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

“…Therefore, the leaky sites of Fig. 5(a) located near the drain should be related to the traps created by impact ionization (I ion ) caused by hotcarriers [15]. On the other hand, those leaky sites located close to the source should have been created by the highelectric field applied to the oxide (E ox ) during the CHC stress, which can induce NBTI damage as well [14].…”

“…In both cases, the stress time was 200 s. Other transistors, acting as a reference, were not stressed. In the case of CHC stress, the voltage configuration (V G = V D ) is the most damaging stress condition for pMOSFETs [14], [15] because it provokes a larger hole injection into the oxide [15]. A current compliance of 1 mA was fixed during the stress.…”

Channel-hot-carrier degradation of strained MOSFETs: A device level and nanoscale combined approach

“…Transistors with different channel lengths (L ¼ 0.13, 0.5, 1, and 3 lm) and 1 lm width were considered. Some samples were subjected to CHC stress by applying V G ¼ V D ¼ À2.6 V for 200 s keeping the other terminals grounded 15 and some other samples were not stressed (fresh samples). Although strain can result in lower external resistance leading to higher internal bias for the same external voltages (compared to nonstrained devices), since the focus of the work is to perform a reliability comparison between both technologies, CHC degradation was induced at the same voltages.…”

Fabrication of a nano-scaled tri-gate field effect transistor using the step-down patterning and dummy gate processes

“…The hot carriers (electrons in NMOS and holes in PMOS) are trapped within the gate insulator during the operation, making the device V th increased. For the given effective channel length, such effect must be more significant in NMOS, where the electron mobility is higher than the hole mobility in the Si channel; as such, the higher hot-carrier generation must be higher in the NMOS device than in the PMOS device [17]. In Fig.…”