2019
DOI: 10.1088/1361-6641/aafdbd
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Characteristics of Al2O3/native oxide/n-GaN capacitors by post-metallization annealing

Abstract: This work investigated characteristics of Al 2 O 3 /native oxide/n-GaN MOS capacitors by postmetallization annealing (PMA). A native oxide interlayer which composed of εand γ-Ga 2 O 3 phases (Native oxide) and the reduced amount of one (Reduced) on n-GaN were prepared by cleaning only a sulfuric acid peroxide mixture (SPM) and both SPM and buffered hydrofluoric acid, respectively. The effect of trimethylaluminum precursor on removal of a native oxide layer was not observed during Al 2 O 3 deposition using atom… Show more

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Cited by 23 publications
(21 citation statements)
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“…The improved interfacial properties suggests that annealing resulted in the reduction of surface/interface defects or dangling bonds similar to the previously observed trap reduction at the interface between Al 2 O 3 and Ga-polar GaN. [31][32][33] Further investigations will be pursued in the future to provide more physical understanding on the impact of annealing on the interface between AlSiO and N-polar GaN. It is noted that annealing at 370 °C resulted in little additional improvement in the density of trapped charge and near-interface traps with respect to annealing at 320 °C.…”
supporting
confidence: 76%
“…The improved interfacial properties suggests that annealing resulted in the reduction of surface/interface defects or dangling bonds similar to the previously observed trap reduction at the interface between Al 2 O 3 and Ga-polar GaN. [31][32][33] Further investigations will be pursued in the future to provide more physical understanding on the impact of annealing on the interface between AlSiO and N-polar GaN. It is noted that annealing at 370 °C resulted in little additional improvement in the density of trapped charge and near-interface traps with respect to annealing at 320 °C.…”
supporting
confidence: 76%
“…For samples A1, A2, A3, B2, and C2 in Table I, the electrical characteristics of devices fabricated using the same process have been described in detail in our previous papers; 14,17,18 the data are summarized in Table II. As shown in Table II, the devices used in the present study exhibit various electrical characteristics.…”
Section: Methodsmentioning
confidence: 99%
“…[14][15][16][17] Therefore, the minimization of trap states at the interface is a critical issue for GaN-based MIS-HEMTs. Although a reduction of the interface trap density (D it ) has been reported after various surface treatments and postdeposition annealing, [6,[18][19][20][21][22][23][24] still few reports have dealt with the effects of surface and postdeposition treatments in terms of D it and their related implications on V th stability during forward gate bias stress conditions.…”
Section: Introductionmentioning
confidence: 99%