Characteristics of Cracking Failure in Microbump Joints for 3D Chip-on-Chip Interconnections under Drop Impact

Abstract

With the rapid development of microelectronics packaging and integration, the failure risk of micro-solder joints in packaging structure caused by impact load has been increasingly concerning. However, the failure mechanism and reliability performance of a Cu-pillar-based microbump joint can use little of the existing research on board-level solder joints as reference, due to the downscaling and joint structure evolution. In this study, to investigate the cracking behavior of microbump joints targeted at chip-on-chip (CoC) stacked interconnections, the CoC test samples were subjected to repeated drop tests to reveal the crack morphology. It was found that the crack causing the microbump failure first initiated at the interface between the intermetallic compound (IMC) layer and the solder, propagated along the interface for a certain length, and then deflected into the solder matrix. To further explore the crack propagation mechanism, stress intensity factor (SIF) of the crack tip at the interface between IMC and solder was calculated by contour integral method, and the effects of solder thickness and crack length were also quantitatively analyzed and combined with the crack deflection criterion. By combining the SIF with the fracture toughness of the solder–Ni interface and the solder matrix, a criterion for crack deflecting from the original propagating path was established, which can be used for prediction of critical crack length and deflection angle for the initiation of crack deflection. Finally, the relationship between solder thickness and critical deflection length and deflection angle of main crack was verified by a board level drop test, and the influence of grain structure in solder matrix on actual failure lifetime was briefly discussed.

Introduction of non-linear fracture mechanics in the modelling of a flip-chip component under drop impact

“…These numerical approaches most commonly use equivalent stresses and plastic strains as indicators of high-risk failure areas (Yang and Meguid, 2013; Gharaibeh et al , 2019). The introduction of linear fracture mechanics in numerical drop test models is considered a more reliable approach for estimating the mechanical response of electronic microcomponents during the drop test (Liu et al , 2022). However, the elastoplastic behaviour of solder bumps makes the use of linear fracture mechanics inaccurate, and the introduction of non-linear fracture mechanics becomes essential.…”

Thermal Induced Interface Mechanical Response Analysis of SMT Lead-Free Solder Joint and Its Adaptive Optimization

“…They found that cracks not only occur at the interface between the solder and the land but also on the solder and the land itself. Zhen Liu et al studied the crack behavior of chip on chip (COC) stacked interconnection microbump joint under drop impact load [4]. It was found that the crack leading to microbump failure first began at the interface between the IMC layer and solder.…”

Editorial for the Special Issue “MEMS Packaging Technologies and 3D Integration”

“…Moreover, package-level system-on-packaging can integrate optics, wireless communication, and power module along with MEMS and IC on a common package. For the packaging and integration explained earlier, interconnection techniques have been important as the packaging size determines the cost of the final product [ 20 , 21 , 22 ]. Interconnect techniques frequently used for MCM packaging are wire-bonding, solder balls, metal stud bumps, and ACF (Anisotropic Conductive Film).…”