Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers

Kola, Sekhar Reddy; Li, Yiming; Thoti, Narasimhulu

doi:10.23919/sispad49475.2020.9241603

Cited by 18 publications

(8 citation statements)

References 10 publications

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“…Also, the D5 is able to maintain the lowest I OFF as the dual-k spacer offers high conduction band energies, which tends to offer lower values of I OFF . 33 Further, The switching ratio (I ON /I OFF ) is a very crucial metric when deciding the device's capability towards logic applications. Usually, switching ratios greater than 10 6 are preferred for logic applications.…”

Section: And Analog/rf Analysismentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

ECS J. Solid State Sci. Technol.

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For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures

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Section: And Analog/rf Analysismentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

ECS J. Solid State Sci. Technol.

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“…Recently, silicon nanosheet devices have attracted a significant increase in interest, both for use in integrated nanoscale electronics and for studying fundamental properties in small scales [ 1 , 2 , 3 , 4 ]. In order to achieve reliable devices or test structures at nanoscale dimensions, it is necessary to control doping levels on silicon nanosheets and to reduce leakage power.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation Investigation of Ferroelectric-Based Electrostatic Doping for Tunnelling Field-Effect Transistor

et al. 2023

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In this paper, a novel ferroelectric-based electrostatic doping (Fe-ED) nanosheet tunneling field-effect transistor (TFET) is proposed and analyzed using technology computer-aided design (TCAD) Sentaurus simulation software. By inserting a ferroelectric film into the polarity gate, the electrons and holes are induced in an intrinsic silicon film to create the p-source and the n-drain regions, respectively. Device performance is largely independent of the chemical doping profile, potentially freeing it from issues related to abrupt junctions, dopant variability, and solid solubility. An improved ON-state current and ION/IOFF ratio have been demonstrated in a 3D-calibrated simulation, and the Fe-ED NSTFET’s on-state current has increased significantly. According to our study, Fe-ED can be used in versatile reconfigurable nanoscale transistors as well as highly integrated circuits as an effective doping strategy.

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“…It exhibits excellent short channel control and improves the performance of the transistor at reduced gate length. It also provides more conducting channels, improved power performance, and better area scaling compared to its other competitor transistors such as FinFET and nanowire [8][9][10][11]. However, nanoscale devices are suffered from different kinds of fluctuations that cause variability in their electrical characteristics [12][13][14][15] and the miniaturization increases the device sensitivity to microscopic perturbation.…”

Section: Introductionmentioning

confidence: 99%

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

Butola

Kola

2022

IEEE Access

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The sensitivity of semiconductor devices to any microscopic perturbation is increasing with the continuous shrinking of device technology. Even the small fluctuations have become more acute for highly scaled nano-devices. Therefore, these fluctuations need to be addressed extensively in order to continue further device scaling. In this paper, we mainly focus on three intrinsic parameter fluctuation sources, work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF) for gate-all-around (GAA) silicon nanosheet (NS) MOSFETs. Generally, the effect of these fluctuations is analyzed using a time-consuming device simulation process. A machine learning (ML) based powerful and efficient artificial neural network (ANN) model is used to accelerate this process. Firstly, the effects of fluctuation sources are analyzed individually by using the ANN model and results have been presented that show the WKF variations dominate the threshold voltage (VTH), off-state current (IOFF), and on-state current (ION) variations among other fluctuation sources. Next, we examine the combined effect of all three fluctuation sources. It is crucial because considering only one fluctuation can result in unexpected variations due to other fluctuations present in the device. Therefore, the ANN model is used to estimate the combined effects as well. The results show that the proposed model predicts the outputs with an R 2 -score of 99% and an error rate of less than 1%. In addition, the ML is also utilized to calculate the permutation importance of input variables as a measure to investigate the contribution of each fluctuation source.

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Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers

Cited by 18 publications

References 10 publications

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Modeling and Simulation Investigation of Ferroelectric-Based Electrostatic Doping for Tunnelling Field-Effect Transistor

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

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