Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS

Kar, Anirban; Parihar, Shivendra Singh; Huang, Jun Z.; Wang, Weike; Imura, Keiichiro; Chauhan, Yogesh Singh

doi:10.1109/ted.2023.3262613

Cited by 2 publications

(7 citation statements)

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“…This aspect is crucial for achieving accurate simulations of HV transistors. In our previous work, we developed a model for the drift resistance and gate overlap charges in the drift region of the HV device [25]. The drift region has been modeled as a function of the voltage drop in the drift region, as shown in (3).…”

Section: Model Descriptionmentioning

confidence: 99%

“…The gate overlap charges model developed in [25] has been used to model the capacitance behavior of the device. The overlap charge (Q OV ) formulation is shown in ( 5) - (7).…”

Section: Model Descriptionmentioning

confidence: 99%

“…The calculated Q OV have been shared between internal nodes di (Q di,OV ) and di1 (Q di1,OV ), as shown in [25]. The Q OV is a function of the bias voltages (V GS and V DS ) and also depends on parameters like flat-band voltage of the drift region VFB, length of the overlap region LOV, and doping of the drift region NDR [25]. All other variables in the equations have the same representation as in [25].…”

Section: Model Descriptionmentioning

confidence: 99%

“…The Q OV is a function of the bias voltages (V GS and V DS ) and also depends on parameters like flat-band voltage of the drift region VFB, length of the overlap region LOV, and doping of the drift region NDR [25]. All other variables in the equations have the same representation as in [25]. These overlap charges give rise to overlap capacitances in the HV device.…”

Section: Model Descriptionmentioning

confidence: 99%

“…In this work, we have exhibited the comprehensive RF characterization and modeling of state-of-the-art, production-level 14/16 nm FinFET-based LDMOS (Fin-LDMOS) devices along with their LV FinFET counterparts, demonstrating their digital and analog performance metrics. The industry-standard Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG) model [24] has been modified to incorporate the impact of overlap charges and drift resistance of the extended drain region of the HV device [25]. This enhancement enables the model to accurately represent the DC, RF, and large-signal characteristics of HV devices.…”

Section: Introductionmentioning

confidence: 99%

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Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Kar,

Parihar,

Huang

et al. 2024

IEEE J. Electron Devices Soc.

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Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

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Section: Model Descriptionmentioning

confidence: 99%

“…The gate overlap charges model developed in [25] has been used to model the capacitance behavior of the device. The overlap charge (Q OV ) formulation is shown in ( 5) - (7).…”

Section: Model Descriptionmentioning

confidence: 99%