Hot Carrier Degradation in Semiconductor Devices 2014
DOI: 10.1007/978-3-319-08994-2_11
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Characterization and Modeling of High-Voltage LDMOS Transistors

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Cited by 5 publications
(3 citation statements)
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“…By applying Eqs. (3)(4) separately to the gate-to-source (forward current if) and gate-to-drain (reverse current ir) sides, the drain current (5) is calculated as the difference between forward if and reverse current ir, multiplied by the current normalization factor (2NIDEut 2 CoxW/L) and carrier mobility (). Such normalization relation helps in decoupling transistor sizes or technology dependence, as the normalized drain current is only a function of the device bias voltages (V G , V D , V S ), electrostatic control (NIDE) and temperature.…”
Section: A the I-v Model And Its Implementationmentioning
confidence: 99%
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“…By applying Eqs. (3)(4) separately to the gate-to-source (forward current if) and gate-to-drain (reverse current ir) sides, the drain current (5) is calculated as the difference between forward if and reverse current ir, multiplied by the current normalization factor (2NIDEut 2 CoxW/L) and carrier mobility (). Such normalization relation helps in decoupling transistor sizes or technology dependence, as the normalized drain current is only a function of the device bias voltages (V G , V D , V S ), electrostatic control (NIDE) and temperature.…”
Section: A the I-v Model And Its Implementationmentioning
confidence: 99%
“…S transistor's dimensions shrink without a corresponding reduction of the supply voltage, hot carrier degradation is becoming one of the main reliability concerns for state-of-theart nMOSFETs [1,2]. Both TCAD- [3,4] and compact-modelbased strategies [5,6,7] have been demonstrated for modelling the hot carrier induced device degradation. However, among all these efforts, no detailed investigation of the crucial correlation between the generated interface states and mobility degradation has been reported.…”
Section: Introductionmentioning
confidence: 99%
“…The chapters of Huard [6], Scholten [13], and Schlünder [14] discuss bridging the gap between device and circuit models. Hot carrier damage in various device types (LDMOS, FinFET, SiGe BJTs, and SiGe channel PFETs) is discussed in the chapters of Reggiani [15], Alagi [16], Cho [17], Chakraborty [18], and Franco [19]. The remainder of this chapter will discuss the atomic picture of HCD and bridging the gap from that picture to realistic circuit prediction.…”
Section: Introductionmentioning
confidence: 99%