Characterization and modeling of MOS mismatch in analog CMOS technology

Wong, Shyh-Chyi; Ting, J.K.; Hsu, S. L.

doi:10.1109/icmts.1995.513967

Cited by 17 publications

(1 citation statement)

References 4 publications

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“…The circled regions represent transistor pairs that require matching threshold voltages to function properly. The final step was to quantify the gate oxide thickness effect on Vt [6]. The results were as follows:…”

Section: Discussionmentioning

confidence: 99%

Integration Challenges in Standard CMOS with Multiple Gate Oxide Thicknesses

Naughton

Towner

2009

ECS Trans.

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Following the prototype release of an automotive, dual gate oxide, and high voltage process, yield problems were observed on an intermittent basis. An investigation was made into a temperature sense circuit and a differential input of a unity gain operational amplifier used for I/O circuitry. The problem was isolated to a bimodal distribution of threshold voltage values for standard gate oxide thickness transistor test structures. When all such structures on the wafer were electrically probed, their distribution of failures was found to be mostly random. Curiously, this mismatch was consistent with a small increase in gate oxide thickness but not observed in the single gate technology. Microscope inspection following etchback of oxide from standard gate regions provided evidence of water spotting and damage to active areas. Process changes were implemented to minimize this damage. Subsequent lots yielded well and matching problems were eliminated.

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Section: Discussionmentioning

confidence: 99%

Integration Challenges in Standard CMOS with Multiple Gate Oxide Thicknesses

Naughton

Towner

2009

ECS Trans.

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Solving Static and Dynamic Performance Limitations for High Speed D/A Converters

Bosch

Steyaert

Sansen

2003

Analog Circuit Design

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In this paper the factors determining the static and the dynamic performance of a current-steering CMOS D/A converter will be discussed. The impact of these factors will be converted in some design guidelines that have to be implemented in order to realize a D/A converter with a state-of-the-art performance.The recent growth of the telecommunication market pushes the designer to put an increasing amount of effort in the integration of digital and analog systems on one chip. Consequently, the interface between these systems is becoming one of the most challenging blocks to design in the telecommunication devices of today. High performance D/A converters find applications in the area of broadband and wireless communications. Because they are inherently fast and cost effective, CMOS current-steering D/A converters are the ideal candidates for such applications. Until a few years ago, open literature used to mention mainly static specifications of D/A converters [1,2]. Recent publications [3,4,5] have revealed that a combination of a high update rate, a high

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