Characterization and modeling of substrate trapping in HEMTs

Abstract

We present a novel and simple model of FET trapping based on a study of HEMTs using pulse techniques. This model accounts for the observed variation of extent of gate lag with bias and step potentials, and the variation of gate-lag time constant with drain potential. Because both charge capture and emission are accounted for, the model is appropriate for the simulation of both large-signal and small-signal dynamics. The model is verified by comparison with large-signal transient measurements and is consistent with small-signal gain measurements.

Study of self-heating in GaAs pHEMTs using pulsed I-V Analysis

“…3(b)) highlights a sub firstorder drain current reduction with time, with a time constant that is common to all traces. This is indicative of self-heating [10], and distinct from trapping effects which are generally first-order phenomena [11]. Furthermore, before the onset of impact ionization, there is no indication of significant drain bias dependent dispersion that is characteristic of trapping.…”