Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology

Parent, Samuel; Vachon, F.; Gauthier, Valérie; Paquette, Alexandre; Deschamps, Jacob; Rossignol, T.; Arsenault, Philippe; Paulin, Caroline; Lemay, Joel; Roy, N.; Cote, M.; Dupont, D.; Martel, Stéphane; Dautet, H.; Charlebois, Serge A.; Pratte, J.‐F.

doi:10.1109/icmts50340.2022.9898180

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…A single-channel prototype PCB was first designed to test the impact of using probes instead of wirebonds (Fig. 8a) [27]. To minimize the PCB size and reduce cabling, the ROIC is used in its default mode (i.e.…”

Section: B Wafer-level Testingmentioning

confidence: 99%

Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes

Parent,

Vachon,

Gauthier

et al. 2024

IEEE J. Electron Devices Soc.

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When developing a technology based on singlephoton avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.

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Section: B Wafer-level Testingmentioning

confidence: 99%

Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes

Parent,

Vachon,

Gauthier

et al. 2024

IEEE J. Electron Devices Soc.

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“…All channels on the ASIC are ready for 3D integration with the SPAD wafer designed and fabricated by Sherbrooke and Teledyne DALSA Semiconductor (TDS), Bromont, Canada 6 . 7 To enable realistic testing of the electronics without assembling the final SPAD array, the readout ASIC includes a row of 64 CMOS SPADs. The ASIC offers three different outputs (Fig.…”

Section: Architecturementioning

confidence: 99%

Fast neutron radiography-based on single-photon digital photosensor: concept and demonstration

Pratte,

Deslandes,

Rossignol

et al. 2023

Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XXV

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For decades, fast neutron radiography performed using pulse-counting detectors employed PMTs coupled to plastic scintillator pixel arrays. SiPM-based systems are now sought to replace fragile PMTs, but conventional, "analog" SiPMs suffer from intrinsic limitations which limit their achievable performance. Among these limitations, a complete analog readout and digitizer chain is required, a counterintuitive approach when considering that the single-photon avalanche diode (SPAD), the basic unit cell of SiPMs, is a Boolean detector providing digital detection at the sensor level. This paper outlines a new concept for neutron radiography instrumentation by using photon-to-digital converters (PDCs, aka digital SiPMs), a fully digital solution to sense the scintillation light.

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“…The 3D PDC consists of a single-photon avalanche diode (SPAD) array vertically integrated with a CMOS readout layer where each SPAD is connected individually to its quenching circuit. The 3D integration process of the PDC is done at wafer-level to allow large-scale manufacturing [14,15]. For large-scale experiments, PDCs will be assembled in tiles to increase the photosensitive area and to facilitate system integration into photodetection modules (PDM).…”

Section: Introductionmentioning

confidence: 99%

A 3D Photon-to-Digital Converter Readout for Low-Power and Large-Area Applications

Rossignol,

Roy,

Parent

et al. 2024

Preprint

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The new trend in large area noble liquid experiments is to measure the scintillation light with photodetectors and their electronics inside the active volume. Compared to the typical approach of using silicon photomultipliers (SiPM) with the analog readout chain to an analog-todigital converter, this paper presents a new 3D photon-to-digital converter (PDC) readout that takes advantage of the binary nature of the single-photon avalanche diode. The readout contains 4096 pixels over 25 mm 2 , each including a 3D bonding pad and a quenching circuit. The readout features three different outputs : a fast flag to get the timestamp of each event from an external time-to-digital converter, a digital sum to retrieve the number of pixels triggered during an event and an analog monitor to generate an analog SiPM-like output. The analog monitor is also used to validate the two former digital outputs. The readout also includes 61 2D CMOS SPADs for validation purpose prior to the final 3D integration with a Teledyne DALSA custom SPAD array. As a first system integration toward large-area detector applications, a mini-tile of 2 × 2 readouts has been developed to test all the functionalities. The measured single-photon timing resolution ranges from 72 to 93 ps FWHM across the mini-tile SPAD channels population (i.e. 4 × 61 channels). The flag timing resolution is below 95 ps RMS, which includes the contribution of the optimized flag H-tree with an additional trigger tree to replace the 3D SPAD array for 2D testing. Once bonded with the 3D SPADs, the trigger tree won't be required to measure the flag timing resolution. With the removed contribution of the trigger tree, the estimated flag timing resolution should be below 45 ps RMS.The benefits of the digital sum output depend on the application, and this paper focuses on two cases. First, a low-power coincidence scheme for the nEXO liquid xenon experiment, leading to a power consumption as low as 140 µW per PDC. On the other hand, with a finer sampling mode of the scintillation light for pulse shape discrimination in liquid argon, the power consumption remains below 100 µW per PDC. Overall, this readout is designed as a replacement for a typical analog SiPM chain, without any compromise on the performances.

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Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology

Cited by 4 publications

References 6 publications

Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes

Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes

Fast neutron radiography-based on single-photon digital photosensor: concept and demonstration

A 3D Photon-to-Digital Converter Readout for Low-Power and Large-Area Applications

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