Characterization and parameterized generation of synthetic combinational benchmark circuits

Hutton, Mike; Rose, Jonathan; Grossman, J. P.; Corneil, Derek G.

doi:10.1109/43.728919

Cited by 52 publications

(74 citation statements)

References 15 publications

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“…To remedy this, we have developed a synthetic benchmark generation technique suitable for the designs which we would like to see. There have been several attempts at generation of realistic synthetic benchmark circuits [DD96,HRGC98,SDC99], but all of these methods use particular features which reflect gate-level designs, rather than the macroblock examples we would like.…”

Section: Synthetic Benchmarksmentioning

confidence: 99%

“…We have thus taken the method of [HRGC98] and modified it to reflect our goals. As in the original method, distributions of various quantitative metrics are extracted from a "seed" design, and these parameters are used to randomly generate new designs which have similar characteristics.…”

Section: Synthetic Benchmarksmentioning

confidence: 99%

“…All but the last characteristic is generated directly from the seed design; in order to generate designs with the correct distribution of cycles, we use a ripup-and-retry technique similar to [HRGC98]. Algorithm 3.1 shows the algorithm we use for this process.…”

Section: Synthetic Benchmarksmentioning

confidence: 99%

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Integration of Physical Design and Sequential Optimization

Chong¹

2006

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Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. This work examines the interaction between the physical design of digital integrated circuits and sequential optimization techniques used for performance enhancement. In particular, the integration of floorplanning and placement with retiming and clock skew scheduling is explored. A theoretical result is given which addresses the computational complexity of circuit partitioning under constraints derived from sequential optimization; this motivates the need for heuristic approaches to the related placement problem. Another theoretical result provides a characterization of the feasible retimings of a sequential circuit; this result is used to motivate an effective method for floorplanning integrated with sequential optimization. Practical techniques for using sequential slack to drive standard-cell placement are shown here; experiments demonstrate significant improvement in final design performance using these methods. Another part of this work examines how the role of sequential optimization and physical design changes when the design allows for asynchronous or latency-insensitive communication between modules. A theoretical result relating to the problem of clock tree implementation for clock skew scheduling under process variation is given. Finally an experimental technique for floorplanning using nonlinear programming is demonstrated. All rights reserved.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Integration of Physical Design and Sequential

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Section: Synthetic Benchmarksmentioning

confidence: 99%

Section: Synthetic Benchmarksmentioning

confidence: 99%

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Integration of Physical Design and Sequential Optimization

Chong¹

2006

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“…When an equivalence class is based on the extracted characteristics of an existing seed benchmark circuit, we call the artificially generated members of the same class "clone-circuits" of the original. The work reported on in this paper formalizes and builds upon previous work [4,5,6,7] in which we created two tools: CIRC, a tool to analyze netlists and extract the properties of interest, and GEN, a tool to generate a new circuit given a set of properties. In the previous work we used pairwise comparison of clone circuits to validate the generation tool, but did not make formal definitions of clones or analyze the behaviour of equivalence classes induced by clones.…”

Section: Introductionmentioning

confidence: 99%

“…al. [4,5,6,7] have described methods and a tool for generating circuits subject to a number of statistical properties about the physical nature of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Equivalence classes of clone circuits for physical-design benchmarking

Hutton

Rose

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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To provide a better understanding of physical design algorithms and the underlying circuit architecture they are targeting, we need to exercise the algorithms and architectures with many benchmark circuits. The lack of existing benchmarks makes us consider the automatic generation of netlists.In this paper, we formally define the equivalence class of circuit "clones" of a given seed circuits, based upon physical properties of the seed circuit's netlist graph. Using these equivalence classes of circuits, a given seed circuit can be used to generate many similar circuits.A more finely grained statistical analysis of algorithm behaviour can then be obtained from using the multiple benchmarks than would be available from using the seed benchmark alone.

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A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

Theodoridis¹,

Soudris²,

Vassiliadis³

Fine- And Coarse-Grain Reconfigurable Computing

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According to the granularity of configuration, reconfigurable systems are classified in two categories, which are the fine-and coarse-grain ones. The purpose of this chapter is to study the features of coarse-grain reconfigurable systems, to examine their advantages and disadvantages, to discuss critical design issues that must be addressed during their development, and to present representative coarsegrain reconfigurable systems that have been proposed in the literature.Current and future applications are characterized by different features and demands, which increase the complexity of developing systems to implement them. The majority of contemporary applications, for instance DSP or multimedia ones, are characterized by the existence of computationally-intensive algorithms. Also, high speed and throughput are frequently needed since real-time applications (e.g. video conferencing) are widely-supported by modern systems. Moreover, due to the wide spread of portable devices (e.g. laptops, mobile phones), low-power consumption becomes an emergency need. In addition, electronic systems, for instance, consumer electronics may have strict size constraints, which make the silicon area a critical Controller CGRU CGRU CGRU CGRU CGRU CGRU Programmable Interconnections Config. Mem.

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Characterization and parameterized generation of synthetic combinational benchmark circuits

Cited by 52 publications

References 15 publications

Integration of Physical Design and Sequential Optimization

Integration of Physical Design and Sequential Optimization

Equivalence classes of clone circuits for physical-design benchmarking

A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

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