Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Antolini, Alessio; Scarselli, Eleonora Franchi; Gnudi, A.; Carissimi, Marcella; Pasotti, M.; Romele, Paolo; Canegallo, R.

doi:10.3390/ma14071624

Cited by 15 publications

(10 citation statements)

References 31 publications

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“…IMC can be realized using Static Random-Access Memory (SRAM) [36], Dynamic RAM (DRAM) [37], and Non-Volatile Memories (NVMs) including Resistive RAM (ReRAM) [38], Phase Change Memory (PCM) [39], STT-MRAM [19], Spin-Orbit Torque MRAM (SOT-MRAM) [29], and other emerging memory devices [18]. NVMs outperform SRAM and DRAM with near-zero leakage power and the non-volatile property of the stored data [40].…”

Section: A Non-volatile Memory and In-memory-computingmentioning

confidence: 99%

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Convolutional Neural Networks (CNNs) demonstrate excellent performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity than BWNs, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of activations and weights and increase the parallelism across memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with a State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% average sparsity.

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Section: A Non-volatile Memory and In-memory-computingmentioning

confidence: 99%

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…. To this purpose, 960 PCM cells, belonging to 80 different WLs, have been programmed with a dedicated iterative algorithm [10] with four different conductance levels. Then, in accordance with (5), all but the i-th input 𝑥 !…”

Section: A Evaluation Of Conductance Time Drift Compensationmentioning

confidence: 99%

An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift Compensation

Antolini

Lico

Scarselli

et al. 2022

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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This paper presents an integrated peripheral unit interfaced to an embedded Phase-change Memory (ePCM) macrocell, with the aim of adding Analog In-memory Computing (AIMC) feature without any modifications to the internal structure of the memory array. The testchip has been designed and manufactured in a 90-nm STMicroelectronics CMOS technology. The unit allows the execution of signed Multiply and Accumulate (MAC) operations at the edge of the memory array exploiting the physical characteristics of memory devices. I-V characteristic non-linearity and transconductance time drift of PCM cells are overcome through a regulated bitline readout circuitry with time-coded inputs, along with a drift compensation technique based on a conductance ratio. Measurements results show 1-σ accuracy of 95.56% in MAC operations, whose decrease in time is roughly negligible at room temperature and is less than 1% after 24 hours at 85°C bake.

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“…Among the state of the art, several strategies to program cells to a specific conductance are proposed [12]- [14]. In this study, the programming algorithm employed in [15] has been exploited to program the 𝑛 " cells for each one of the above-mentioned normalized conductance targets. Upon the definition of a conductance target interval by specifying its mean value 𝑔 & and relative tolerance 𝛥𝑔, each cell is first stimulated with a start SET and a start RESET pulse, which both have a high amplitude current, as they grant better temporal drift retention [12][15].…”

Section: B Experimental Proceduresmentioning

confidence: 99%

Phase-change memory cells characterization in an analog in-memory computing perspective

Antolini

Lico

Scarselli

et al. 2022

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

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Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

Cited by 15 publications

References 31 publications

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift Compensation

Phase-change memory cells characterization in an analog in-memory computing perspective

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