Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Abstract

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize them, retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

ATLAS toward the High Luminosity era: challenges on electronic systems

“…ATLAS electronics system challenges for HL-LHC Carlos A. Solans Sánchez SEUs, they will be placed outside of the detector volume, where 1 SEU per day per VTRX+ is still expected and mitigated by continuous monitoring. Additionally the Pixel modules require a custom Gigabit Receiver Chip (GBCR) [14] to recover the signal after the electrical transmission over 6 m of custom twisted pairs of data at 4×1.28 Gb/s. The measured jitter (peak to peak) at the output of the GBCR is 94 ps which is compatible with the requirements of the lpGBT.…”

“…For the ATLAS experiment [1], this means a Total Ionizing Dose (TID) above 10 MGy and a Non-Ionizing Energy Loss (NIEL) of 10 16 1-MeV-n/cm 2 in the parts of the detector closest to the beam pipe, where the usage of custom ASIC designs is expected, and a TID ∼ 100 Gy and 10 14 1-MeV-n/cm 2 NIEL in the outer regions, that will allow the use of more flexible FPGA designs combined with single-point-failure-free engineering. In both cases qualification against TID, including surface effects and transistor damage, and single-event-effects (SEE) including single event upsets (SEU) and single latch-up events (SEL) is required.…”

ATLAS ITk Pixel Detector Overview

“…These links are shown in Figure 13 as kapton-copper flexes (Type-0 services) between module and patch panel 0 (PP0). From PP0 data is transmitted through custom Twinax cables to the optoboard [17], where electrical signal is recovered by the Gigabit Receiver Chip [18] and is aggregated and converted to optical signal through the low-power Gigabit Transceiver (lpGBT [19]) and VTRx [20] before being sent off detector to the readout.…”

Characterization of 3.2 Gbps readout in 65 nm CMOS technology

“…With the increasing number of pixel counters and increasing spatial resolution of the sensors, the uplink throughput requirements are out of range for traditional digital readout techniques. The designs must achieve multi-gigabit data rates by using serial data transmission [4,5].…”