Chemical-mechanical polishing (CMP) has emerged as the premier technique for achieving both local and global planarizations in silicon integrated circuit (Si IC) manufacturing. With the transition of Si IC fabrication industry to using sub-half-micron devices in the late 1990s, the CMP market size has grown rapidly, from about $300-400 millions in 1997 to over $2 billions in 2002 and is predicted to be over $3 billions by 2008 [1]. Among the $3 billions, roughly half belongs to equipment related to CMP, such as polishers and metrology tools. The other half is associated with materials such as slurries and pads ( Fig. 2.1). Another recent market research study predicts the CMP slurry/ pad market size to be around $1.8 billions by 2009 presenting a CAGR of 16% and 17% for slurries and pads, respectively, driven primarily by the rise of copper CMP and transition to 300 mm wafer size (Fig. 2.2) [2]. Similar to other semiconductor sectors, the CMP community faces constant challenges in the identification, selection, characterization, and qualification of materials. They are vital to the success of implementing and sustaining the CMP processes in the ever-competitive global semiconductor manufacturing environment.To put the topic in perspective, the market size of the materials related to semiconductor manufacturing is now over 10 billions USD [3]. Among these key materials, the sum of CMP slurry and pad is over 11%, which is approaching the combination of photoresist and stripping chemicals (Fig. 2.3). On the one hand, this is a strong indication that CMP technology has become a Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li