Characterization of a RISC-V System-on-Chip under Neutron Radiation

Abstract

Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip

“…This result is shown in Table III, which classifies the executions as correct benchmark result, benchmark finished with error, and benchmark execution failed to finish. This table also compares these results with our previous work [17], in which we tested a similar setup but had fewer beam-time and number of events. Therefore, the results of this work have enhanced confidence margins.…”

“…The work presented promising results demonstrating that the circuitry added to the processor increased its reliability by reducing error propagation. In [17], the initial characterizations in a radiation environment were performed, corroborating the propositions elaborated using fault injection and presenting further challenges. In the present work, we discuss improvements made in the processor's design, present the experimental setup at the irradiation facility, and provide a more detailed analysis of errors rate and classification.…”

“…Table I presents the number of detected errors during the entire test campaign and compares it to the previous work [17]. Although this work has a larger number of detected errors than the previous work (more than four times), the percentage of corrected errors remained very similar.…”

“…We adopted these techniques due to their wide employment in related work [19]- [22]. Also, their combination results in a robust and cost-effective hardening strategy, as shown in [15], [17].…”

“…It is important to note that monitoring these events is always enabled, which allows reporting error rates even when the hardening features are disabled. Since the previous work [17], HARV-SoC received an improvement in the logic implemented for the ECC operation in RAM memory transactions. Now, for each ECC event, the read data is corrected and written back in the concerned memory address.…”