Characterization of AC coupled SOI pixel sensor with pinned depleted diode structure

Dong, Jinmei; Lu, Y.; Wu, Zhigang; Zhou, Yang; Ouyang, Q.

doi:10.1016/j.nima.2022.167204

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2024

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“…CPV-1 and CPV-2 [3] confirmed that small 16 μm × 16 μm pixels using binary readout can achieve a spatial resolution within 3 μm. In CPV-3 [4], extensive testing was conducted on the critical sensing diode structure, known as the Pinned Depleted Diode (PDD) [5], which involved the calibration of the charge collection efficiency and diode capacitance. CPV-4 introduced 3D vertical integration technology, exploring a 3D chip architecture for integrating all the elementary functional blocks into a compact design.…”

Section: Introductionmentioning

confidence: 99%

3D-integrated pixel circuit for a low power and small pitch SOI sensor

Zhou,

Lu,

Zhou

et al. 2024

J. Inst.

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Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor has been developed. Its pixel circuit requires about 120 transistors to implement the analog-digital mixed signal processing functionality within a compact pixel area of 17 μm × 21 μm. By utilizing 3D vertical integration, sensing diode and analog front-end are realized in the lower-tier chip, while hit information storage and sparse readout are achieved in the upper-tier chip, thereby minimizing its pixel size and power consumption. This work presents the pixel circuit design and the test results on the completed 3D chips. The feature of SOI pixel process and the 3D integration are also highlighted in this article.

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Section: Introductionmentioning

confidence: 99%