As pin counts and interconnection densities increase there is growing interest in copper pillar bumps for flip chip and wafer-level packaging. Copper pillars retain their shape in both the x, y and z directions during solder reflow, allowing finer interconnect pitches with predictable standoff heights. The fabrication of copper pillar bumps requires the use of a very thick photoresist layer for the copper electroplating. This photoresist material must be capable of coating, exposing, developing, electroplating and stripping with conventional equipment and standard ancillary process chemicals. In addition, photoresist sensitivity and process bake and development times are critical to minimize the cost of ownership of the lithography cell. For the electroplating process the photoresist profile, plating durability and stripability are important considerations. This study will characterize a novel photosensitive photoresist (Shin-Etsu SIPR 7123M) for a single coat, 55 μm thick copper process for a manufacturing environment. This photoresist has been formulated for enhanced photospeed, ease of stripability and has additives to eliminate the cracking often seen with very thick films. The lithographic performance of the thick positive photoresist will be optimized using a broad band, low numerical stepper. Enhanced process flexibility and productivity will be shown in regards to developer type and no wait times between process steps. Results will show excellent adhesion to copper with no surface treatment and no photoresist popping during exposure. Cross sectional SEM analysis, process latitude, and copper plating performance are used to establish the lithographic capabilities.