Characterization of charge accumulation and detrapping processes related to latent failure in CMOS integrated circuits

Greason, W.D.; Chum, K.

doi:10.1109/ias.1991.178230

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“…Comparison of the SFM topology and surface potential images suggests that localized charge accumulation occurs in the high resistivity passivation prior to an ESD-like event resulting in a dielectric failure. However, ESD-like events can also be non-fatal [3][4][5][6]. High electric field transients can produce shifts in V,and other parameters due to oxide and interface trapped charge.…”

Section: Degradation Mechanismmentioning

confidence: 99%

Focused Ion Beam Induced Effects on MOS Transistor Parameters

Abramo¹,

Antoniou²,

Campbell

et al. 1999

International Symposium for Testing and Failure Analysis

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We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

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Section: Degradation Mechanismmentioning

confidence: 99%