Characterization of Deep Levels in N-Type Si Epitaxial Layer

Abstract

A deep level of E c-0.46 eV (E1) was observed in commercially available Si epitaxial layers. The deep level decreased gradually at room temperature and eventually vanished completely 8 months after growth, and new levels, E c-0.08 eV, E c-0.10 eV, E c-0.14 eV and E c-0.21 eV, were observed. After annealing at 750° C, E1 level appeared again and all of the new levels disappeared. All levels, including E1, disappeared upon high-temperature annealing (>1000° C) in a O2 ambient. It was confirmed that these deep levels were due to contamination by Fe in epitaxial layer.

Deep levels in silicon–oxygen superlattices

“…The deep levels observed in the depletion region of the silicon epi references should be distinguished from those in the Si-O SL samples. Most DLTS studies in the past on silicon epi layers are concerned with as-deposited n-type silicon [32][33][34], while for p-Si, a band of states in the upper half of the bandgap at E C -0.3 eV has been reported, corresponding with the Si-Si interface [35]. Here, a negligible density of traps is found for a pulse in depletion (e.g., the +2 V to +1 V spectrum in figure 5(a)), indicating the good quality of the pre-epi cleaning and the CVD processes.…”

Comparison between Si/SiO2 mid‐gap interface states and deep levels associated with silicon‐oxygen superlattices in p‐type silicon

“…As CVD is performed at rather low temperatures, one can expect some incorporation of a non-equilibrium density of native point defects, i.e., vacancies and self-interstitials. Most DLTS studies on silicon epi layers in the past are concerned with as-deposited n-type silicon [15][16][17], while for p-Si, a band of minority electron traps in the upper half of the bandgap at E C -0.3 eV has been reported, corresponding with the Si-Si interface [18]. This was confirmed on in situ B-doped p + epi layers deposited on n-type Cz Si substrates by CVD [19,20].…”